Jinman Yang

CMOS-Compatible SOI MESFETs With High Breakdown Voltage

The authors demonstrate that silicon-on-insulator (SOI) MESFETs can be fabricated alongside SOI CMOS with no changes to the foundry process flow. The MESFETs operate in depletion mode with a threshold voltage of -0.6 V for a gate length of 0.6 mum. The breakdown voltage of the MESFETs greatly exceeds that of the CMOS devices and varies in the range of 12-58 V depending upon the channel access length, i.e., the distance from the edge of the gate to the edge of the drain region. For MESFETs with a gate length of 0.6 mum and an access length of 0.6 mum, the peak cutoff frequency exceeds 7 GHz. The maximum available gain increases with drain bias and values of fmax range from 17 GHz at VDD = 2 V to 22 GHz at VDD = 8 V

SILICON-BASED INTEGRATED MOSFETS AND MESFETS: A NEW PARADIGM FOR LOW POWER, MIXED SIGNAL, MONOLITHIC SYSTEMS USING COMMERCIALLY AVAILABLE SOI

Metal Semiconductor Field Effect Transistors fabricated using compound semiconductor materials have important applications in high-speed/low-noise communication systems. However, their integration densities are low compared to silicon technologies, and it is difficult to combine them with conventional CMOS for single-chip, mixed-signal circuit applications. In this paper we describe how silicon-on-insulator MESFETs can be fabricated alongside conventional MOSFETs using a commercially available silicon-on-insulator foundry. The process flow for the integrated MOSFETS and MESFETs is presented. Measurements from MESFETs fabricated using a commercial foundry demonstrate good depletion-mode device operation. The measured data confirms a square-law behavior for the saturated drain current, which can be reproduced using readily available MESFET models for Spice circuit simulation. The Spice model is applied to a simple differential-pair amplifier and the modeled results compared to measured data.

High-frequency performance of subthreshold SOI MESFETs

Results from silicon-on-insulator (SOI) MESFETs designed for subthreshold operation are presented. The transistors have subthreshold slopes as low as 78 mV/dec and off-state drain currents approaching 1 pA//spl mu/m. Drain current saturation can be achieved with drain voltages of less than 0.5 V and with output impedance>100 M/spl Omega//spl middot//spl mu/m. The cutoff frequency of a 500-nm gate length device exceeds 1 GHz at currents significantly less than 1 /spl mu/A//spl mu/m. These results suggest that subthreshold SOI MESFETs might have useful applications in mixed-signal, micropower circuit design.

Total dose radiation response of CMOS compatible SOI MESFETs

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi/sub 2/ Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The transistors have been irradiated with 50 keV X-rays to a total ionizing dose in excess of 1 Mrad(Si). After irradiation the threshold voltage of both the top Schottky gate and the back MOS gate shift to more negative values. The shift in threshold is attributed to radiation induced fixed oxide charge at the interface between the SOI channel and the buried oxide.

Controlling the threshold voltage of a metal–oxide–semiconductor field effect transistor by molecular protonation of the Si:SiO2 interface

We present results from a hybrid molecular/metal–oxide–semiconductor field effect transistor (MOSFET) structure that is sensitive to the presence of a molecular monolayer on its surface. The device is fabricated from a silicon-on-insulator substrate, and unlike a conventional MOSFET a substrate voltage is used to invert the buried Si:SiO2 interface. This allows the top surface of the silicon to be free of any insulating layers, apart from a thin native oxide that forms on exposure to air. The buried inversion layer is less than 40 nm away from the exposed surface, and the threshold voltage of the device is strongly influenced by the surface potential. Measurements of the drain current as a function of substrate voltage can be accurately reproduced from numerical simulation by treating the charge at the native oxide interface as a fitting parameter. The shift in threshold voltage after molecular attachment can be accounted for by a simple increase in the (positive) fixed oxide charge density, all of the ot...

Shallow source/drain extensions for deep submicron MOSFETs using spin-on-dopants

Spin-on-dopants and rapid thermal processing have been used to form ultra-shallow n/sup +/-p junctions with metallurgical junction depths as shallow as 12 nm as determined by secondary ion mass spectroscopy. The electrical junction depth and the total charge concentration have been measured in the vicinity of the junction using electron holography and are shown to be consistent with activation efficiencies of 80%. The ultra-shallow junctions have been used as the source and drain contacts of sub-100-nm gate length MOSFETs. From electrical measurements, the authors extract a lateral diffusion length for the source and drains that is comparable to the vertical extent of the n/sup +/-p junctions.

High-Voltage CMOS Compatible SOI MESFET Characterization and Spice Model Extraction

A mature and well-established SOI CMOS process has been used to fabricate metal-semiconductor field-effect transistors (MESFETs) that operate in the gigahertz range. These 0.6mum depletion-mode SOI MESFETs exhibit a maximum breakdown voltage of 45V in spite of being fabricated using the standard 3.3V CMOS process. This high voltage capability makes the device a strong contender for applications such as power amplifiers, voltage controlled oscillators and DC-DC converters. DC and RF characterization involving breakdown voltage measurements, S-parameter measurements and small-signal parameter extraction was conducted on the device. We have customized an advanced, commercially available TOM3 SPICE MESFET model to represent the SOI MESFET. Based on extracted small-signal parameters, a simplified method to extract the charge parameters of the TOM3 capacitance model was developed. A diode subcircuit has been proposed to model the breakdown mechanism in the SOI MESFET

SOI low frequency noise and interface trap density measurements with the pseudo MOSFET

Low frequency noise (LFN) is important in analog and digital circuits. In analog circuits it affects the performance of low-noise amplifiers and the phase noise (1) of voltage-controlled oscillators (2). In digital circuits it becomes more important as the supply voltage is reduced and it degrades substrate noise coupling. Low-frequency noise is due to interactions of the channel carriers with oxide/semiconductor interface traps and oxide charges and is very dependent on the quality of the oxide/semiconductor interface and noise measurements can give important information about such interfaces and defects (3). Silicon-on-insulator devices have two oxide/semiconductor interfaces and the bottom interface is generally worse than the top interface. Most LFN measurements are made after MOSFET fabrication, but it is desirable to characterize such materials without fabricating devices. In this paper we discuss silicon-on-insulator (SOI) low-frequency noise and interface trap density measurements using a Ground-Signal-Ground (GSG) pseudo-MOSFET structure with minimum fabrication.

Molecular control of the threshold voltage of an NMOS Inversion layer

We have developed a hybrid molecular-MOSFET structure that is sensitive to the presence of a molecular monolayer attached to its surface. The device is fabricated from a silicon-on-insulator wafer and we use a substrate voltage, Vsub, to invert the buried Si:SiO2 interface. This allows the top surface of the silicon to be free of any insulating layers, apart from a thin native oxide that forms on exposure to air. The buried inversion layer is only a few hundred angstroms away from the exposed surface, and the threshold voltage of the device, Vth, is strongly influenced by the surface potential. A spiropyran monolayer is attached to the surface of the device by means of carboxylic-SiO2 bonding. After attachment of the monolayer, the threshold voltage of the device shifts to more negative values. We explain this result in terms of an increase in the concentration of fixed positive charge at the upper Si:SiO2 interface due to protonation of the surface by the molecular monolayer.

Drain current control in a hybrid molecular/MOSFET device

Abstract We have developed a hybrid molecular/MOSFET, which is sensitive to the presence of a molecular layer attached to its surface. The application of the molecular layer was investigated by observing changes in the threshold current of the device. A significant shift in the threshold voltage was attributed to an increase in the electron charge density in the MOSFET channel, resulting from an increase in the positive fixed charge at the native oxide surface. A numerical simulation supports this conclusion. It is speculated that the molecules protonate the surface of the SiO 2 due to the higher acidity of the molecular groups compared to that of the native oxide. To assess the validity of this hypothesis a series of molecules with similar structure but with different acidities (p K a values) were investigated. Preliminary results showing the systematic variation of Δ V th and p K a are presented.