Trevor J. Thornton

CMOS-Compatible SOI MESFETs With High Breakdown Voltage

The authors demonstrate that silicon-on-insulator (SOI) MESFETs can be fabricated alongside SOI CMOS with no changes to the foundry process flow. The MESFETs operate in depletion mode with a threshold voltage of -0.6 V for a gate length of 0.6 mum. The breakdown voltage of the MESFETs greatly exceeds that of the CMOS devices and varies in the range of 12-58 V depending upon the channel access length, i.e., the distance from the edge of the gate to the edge of the drain region. For MESFETs with a gate length of 0.6 mum and an access length of 0.6 mum, the peak cutoff frequency exceeds 7 GHz. The maximum available gain increases with drain bias and values of fmax range from 17 GHz at VDD = 2 V to 22 GHz at VDD = 8 V

Characterization of nickel Germanide thin films for use as contacts to p-channel Germanium MOSFETs

We have measured the physical properties and resistivity of nickel germanide thin films formed by the rapid thermal annealing of nickel metal on p-type germanium substrates. Rutherford back scattering and high-resolution electron diffraction confirm that the stoichiometry of the resulting nickel germanide film corresponds to NiGe and has an orthorhombic unit cell with dimensions comparable to that of bulk samples. Transmission electron microscopy shows a poly-crystalline film structure with grain size > 0.1 /spl mu/m. The resistivity values for films annealed in the range 350/spl deg/C-500/spl deg/C are comparable to those of metal silicides. Measurements of the specific contact resistance suggest that values approaching 2 /spl times/ 10/sup -7/ /spl Omega/.cm/sup 2/ can be realized using NiGe formed on heavily doped p-type germanium.

Electromigration current rectification in a cylindrical nanopore due to asymmetric concentration polarization

We present experimental measurements of electromigration current through a single cylindrical nanopore. A single cylindrical nanopore with 175 nm diameter was fabricated in silicon in series with two micropores with 2 and 100 microm diameters. Thick electrical double layers (EDLs) (kappa a approximately 1) exhibit current rectification due to asymmetric concentration polarization while thinner EDLs show nearly symmetric conductance. After the electric field is turned off, electrical current is measured and observed due to redistribution of ions in the concentration polarization layer.

SOI MESFETs Fabricated Using Fully Depleted CMOS Technologies

Ultrathin channel metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using fully depleted silicon-on-insulator CMOS foundries with no changes to the process flow. The Schottky gate of the MESFET is formed from a metal silicide that consumes most of the thin ( < 50 nm) FD-SOI channel and fully depletes the remaining underlying silicon. Therefore, unlike partially depleted SOI MESFETs with a thicker silicon layer ( ~ 200 nm), the conducting channel of the FD-SOI MESFET cannot be formed directly under the Schottky gate. Instead, current flow in the FD-SOI MESFET is confined between islands of silicide that deplete the conducting channel in a lateral direction. The FD-SOI MESFETs operate as depletion mode devices with a threshold voltage that can be adjusted by varying the separation between the silicide islands. Both n- and p-channel devices can be realized using the same gate material on a common FD-SOI substrate.

Physics and applications of the Schottky junction transistor

This paper presents the results from numerical simulations of a novel subthreshold transistor configuration. The device uses the input current from a forward-biased Schottky gate to control the larger current flowing in a depleted channel. Analytical approximations are used to derive the current gain of the transistor. The numerical simulations confirm the analytical derivation and show that a 0.5 /spl mu/m gate length device would have a cutoff frequency approaching 10 GHz for supply voltages less than 0.5 V. Possible applications of the device in the areas of micropower analog circuits and ULSI logic are discussed.

Field effect modulation of ionic conductance of cylindrical silicon-on-insulator nanopore array

Results demonstrating the field effect modulation of ionic transport through an array of cylindrical nanopores fabricated in silicon-on-insulator substrates are presented. Pronounced modulation of the conductance is observed at low electrolyte concentrations when the electric double layers within the nanopores are overlapping. A numerical model based on Brownian dynamics reproduces the measured data.

High-frequency performance of subthreshold SOI MESFETs

Results from silicon-on-insulator (SOI) MESFETs designed for subthreshold operation are presented. The transistors have subthreshold slopes as low as 78 mV/dec and off-state drain currents approaching 1 pA//spl mu/m. Drain current saturation can be achieved with drain voltages of less than 0.5 V and with output impedance>100 M/spl Omega//spl middot//spl mu/m. The cutoff frequency of a 500-nm gate length device exceeds 1 GHz at currents significantly less than 1 /spl mu/A//spl mu/m. These results suggest that subthreshold SOI MESFETs might have useful applications in mixed-signal, micropower circuit design.

Scaling SOI MESFETs to 150-nm CMOS Technologies

Metal-semiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT >; 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ~70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg <; 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200-300 nm.

High Field Transport Studies of GaN

We report on experimental and theoretical studies of high field transport in bulk GaN. Theoretically, we have investigated the electron-phonon interaction in this material based on empirical pseudopotential method (EPM) calculations for the bandstructure, together with an empirical valence shell model for the lattice dynamics in cubic GaN. The rigid-ion model is used to calculate the electron-phonon scattering rate for all modes, and to extract a deformation potential for use in high field transport calculations. A full band Monte-Carlo (FBMC) method is used to simulate high field transport in GaN. In the experimental studies, we have fabricated etched constrictions for performing pulse I-V measurements in bulk GaN and GaN/AlGaN heterostructures. The experimentally extracted velocity-field characteristics are in good agreement with transport calculations up to fields as high as 1.5 x 10 5 V/cm, where velocities up to 2.5 x 10 7 cm/s are measured.

Total dose radiation response of CMOS compatible SOI MESFETs

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a silicon-on-insulator (SOI) CMOS process. The MESFETs make use of a TiSi/sub 2/ Schottky gate and display good depletion mode characteristics with a threshold voltage of -0.5 V. The drain current can also be controlled by a voltage applied to the substrate, which then behaves as a MOS back gate. The transistors have been irradiated with 50 keV X-rays to a total ionizing dose in excess of 1 Mrad(Si). After irradiation the threshold voltage of both the top Schottky gate and the back MOS gate shift to more negative values. The shift in threshold is attributed to radiation induced fixed oxide charge at the interface between the SOI channel and the buried oxide.