Jinseok Koh

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup

A low-distortion third-order class-D amplifier that is fully integrated into a 0.18-μ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma (ΔΣ) modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-Ω load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-Ω load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7-4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm2 and achieves a THD+N of 0.018%.

A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process

A discrete-time sigma delta ADC is presented, that filters and decimates by two the input data samples, while providing amplification in its input sampling stage. This compact architecture allows operating preceding blocks at twice the ADCs clock frequency, thus improving the noise performance of the receive channel. The presented approach has been validated and incorporated in a commercial Bluetooth receiver IC, realized in a 1.5 V, 130 nm digital CMOS process.

A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end

A Class-D amplifier (CDA) is best suitable for audio mobile applications due to its high-power efficiency, thus enabling to remove a bulky heat sink. A traditional Class-D amplifier uses a 2-level output switching scheme. There typically exist an external LC filter and a bulky capacitor to block a DC average current and to protect the speaker from the current, which increases the bill of materials. As a remedy, a 3-level switching scheme allows to eliminate the filters, hence helping to reduce the system cost. Moreover, the 3-level switching scheme provides additional benefits of less electromagnetic interference and better power efficiency. The 3-level approach prevails with the help of various modulation techniques such as a pulse-width modulation (PWM) [1,2], a sliding-mode control [3], and a uniform PWM [4] method.

A sigma-delta ADC with decimation and gain control function for a Bluetooth receiver in 130 nm digital CMOS

We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC) architecture was chosen for antialiasing filtering. The decimation-by-two function is realized using divided-by-two clock signals in the antialiasing filter. Antialiasing, gain control, and sampling functions are merged in the sampling network using SC techniques. This compact architecture allows operating the preceding blocks at twice the ADCs clock frequency, thus improving the noise performance of the wireless receiver channel and relaxing settling requirements of the analog building blocks. The presented approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in a 1.5 V 130 nm digital CMOS process. The measured antialiasing filtering shows better than 75 dB suppression at the folding frequency band edge. A 67 dB dynamic range was measured with a sampling frequency of 37.5MHz.

A 66dB DR 1.2V 1.2mW single-amplifier double-sampling 2/sup nd/-order /spl Delta//spl Sigma/ ADC for WCDMA in 90nm CMOS

A single-amplifier double-sampling second-order /spl Delta//spl Sigma/ ADC with 5-level quantization is implemented in 90nm CMOS. To alleviate the capacitor mismatch issues in double sampling techniques, a single capacitor method is introduced, achieving 63dB peak SNDR and 66dB DR in a 1.94MHz bandwidth while consuming 1.2mW from a 1.2V supply.