Jiro Ida

Monolithic Pixel Detector in a 0.15 μm SOI Technology

We describe a new pixel detector development project using a 0.15 μm fully-depleted CMOS SOI (silicon-on-insulator) technology. Additional processing steps for creating substrate implants and contacts to form sensor and electrode connections were developed for this SOI process. A diode test element group and several test chips have been fabricated and evaluated. The pixel detectors are successfully operated and first images are taken and sensibility to β-rays is confirmed. Back gate effects on the top circuits are observed and discussed.

Fully Depleted SOI Technology for Ultra Low Power Digital and RF Applications

Today, various specifications are demanded to LSI, which is indispensable for industry and our life. For example, in the field of mobile equipments, watch and sensor devices in ubiquitous network, low-power-consumption devices are required. On the other hand, in the field of high-end processing, high performance devices are required. Silicon-on-insulator (SOI) devices have various advantages over bulk Si devices in the above-mentioned fields (Colingue, 2004). SOI-based sensors have also been introduced (Wan, 2005). In this paper, aiming for ultra-low-power digital analog and RF applications, we present major characteristics and issues of fully-depleted SOI (FD-SOI), and discuss the approaches to expanding the capability of FD-SOI devices

Undoped thin film FD-SOI CMOS with source/drain-to-gate non-overlapped structure for ultra low leak applications

In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.

SOI pixel developments in a 0.15μm technology

While the SOI (silicon-on-insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and low-power applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of fully-depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15mm FD-SOI CMOS process. We have preformed two multi project wafer (MPW) runs using this SOI process. We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories. Features of these SOI devices and experiences with SOI pixel development are presented.

Consistent dynamic depletion model of SOI-MOSFETs for device/circuit optimization

We report the potential-based SOI-MOSFET model HiSIM-SOI, which solves the three surface potentials of the SOI-device accurately without sacrificing simulation time. The model implements the bias dependent dynamic depletion behavior, shifting between partially-depleted (PD) and fully-depleted (FD) conditions smoothly. It is also demonstrated that the floating-body effect can be accurately captured in a simple way from the calculated surface potentials without the necessity of introducing on additional node. HiSIM-SOI is also verified to correctly reproduce measured data of both body-contact and floating-body devices.

Suppresion of Floating Body Effect in Low Leakage FD-SOI with Fluorine Implantation Technology

In this paper, we report a new method of suppressing the floating body effect (FBE) in low leakage FD-SOI transistor. We applied the fluorine implantation for NFET to supress the floating body effect, keeping low leakage current. The Vt shift of ~300mV is observed and drain induced barrier lowering (DIBL) improves ~100mV/V for L=0.14mum

DC and RF temperature behavior of deep submicron Graded Channel MOSFETs

The superior performance of Graded-Channel MOSFET over classical MOSFET transistors is demonstrated to extend to down scaled channel lengths. While keeping a normal down scaling trend, Graded-Channel devices continue to show favoured static and analog performances in comparison to classical devices. Graded-Channel devices are also characterized in high temperature and high frequency regimes of operation.

Modeling of electron tunneling in SOI-MOSFET and its influence on device characteristics

It is known that the electron tunneling from the valence band (EVB) is enhanced for SOI-MOSFETs with low Vds bias. We have modeled this phenomenon based on the surface-potential description. Our model considers the hole storage, which changes the potential distribution in the substrate. With the developed model it is demonstrated that the EVB effect can be predicted for any measurements accurately. The stored charge results in a 1/f noise enhancement at the same time, which is also well predicted.

High temperature RF behavior of SOI MOSFETs for low-power low-voltage applications

At zero-temperature-coefficient bias points, transistors are known to have stable DC performance with temperature variation. In this work, the RF behavior at those specific bias points is presented in order to provide design guidelines for low-power low-voltage circuits featuring stable RF performance in variable temperature environments and applications. Fully- and partially depleted SOI MOSFETs with and without body contact are analyzed.

Improvement of the tolerance to total ionizing dose in SOI CMOS

According to the CMOS device on SOI substrate (SOI CMOS device), we investigate the influence of holes accumulated in buried oxide film (BOX) under the radiation environment by monitoring leakage current with back bias. We confirmed that the leakage current has the colleration to total ionizing dose (TID). SOI CMOS assumed to be not good on TID, compared to bulk. But, we confirmed the tolerance to TID in SOI CMOS was improved from 200 to 3000 Gy(Si) with the process optimization, which is better than bulk CMOS.