Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Jisoo Kim is active.

Publication


Featured researches published by Jisoo Kim.


Proceedings of SPIE | 2007

Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool

Wooyung Jung; Sang-Min Kim; Choidong Kim; Guee-Hwang Sim; Sung-Min Jeon; Sang Wook Park; Byung-Seok Lee; Sungki Park; Jisoo Kim; Lee-Sang Heon

Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.


Proceedings of SPIE | 2008

Double patterning of contact array with carbon polymer

Wooyung Jung; Guee-Hwang Sim; Sang-Min Kim; Choidong Kim; Sung-Min Jeon; Keunjun Kim; Sang Wook Park; Byung-Seok Lee; Sungki Park; Hoon-Hee Cho; Jisoo Kim

The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning technique and double exposure & etch technique (DEET) 1, the former would be preferable to the latter by the issues of overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line & space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact as well as line & space of 30nm half pitch.


Plasma Sources Science and Technology | 2001

Mass spectrometric and Langmuir probe measurements in inductively coupled plasmas in Ar, CHF3/Ar and CHF3/Ar/O2 mixtures

Jisoo Kim; M. V. V. S. Rao; Mark A. Cappelli; Surendra P. Sharma; M Meyyappan

Absolute fluxes and energy distributions of ions in inductively coupled plasmas of Ar, CHF 3 /Ar, and CHF 3 /Ar/O 2 have been measured. These plasmas were generated in a gaseous electronics conference cell modified for inductive coupling at pressures of 10-50 mTorr and 100-300 W of 13.56 MHz radio frequency (RF) power in various feed gas mixtures. In pure Ar plasmas, the Ar + flux increases linearly with pressure as well as RF power. In mixtures, the Ar + flux decreases with increase in pressure and CHF 3 concentration in the mixture. The loss mechanism for Ar + is attributed to resonance charge exchange (Ar + + CHF 3 → products). Total ion flux in CHF 3 mixtures decreases with increase in pressure and also CHF 3 concentration. Relative ion fluxes observed in the present studies are analysed with the help of available cross sections for electron impact ionization and charge-exchange ion-molecule reactions. Measurements of plasma potential, electron and ion number densities, electron energy distribution function, and mean electron energy have also been made in the centre of the plasma with an RF-compensated Langmuir probe. Plasma potential values are compared with the mean ion energies determined from the measured ion energy distributions and are consistent. Electron temperature, plasma potential, and mean ion energy vary inversely with pressure, but increase with CHF 3 content in the mixture.


Proceedings of SPIE | 2007

A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond

Maaike Op de Beeck; Janko Versluijs; Zsolt Tőkei; S. Demuynck; J.-F. de Marneffe; Werner Boullart; Serge Vanhaelemeersch; Helen Zhu; Peter Cirigliano; Elizabeth Pavel; Reza Sadjadi; Jisoo Kim

Limits to the lithography process window restrict the scaling of critical IC features such as holes (contact, via) and trenches (required for interconnects and double patterning applications). To overcome this problem, contacts or trenches can be oversized during the exposure, followed by the application of a shrink technique. In this work, a novel shrink process utilizing plasma-assisted polymer deposition is demonstrated: a polymer is deposited on the top and sidewalls of photoresist by alternating deposition and etch steps, reducing the dimension of the lithography pattern in a controlled way. Hence very small patterns can be defined with wide process latitudes. This approach is generic and has been applied to both contacts and trenches. The feasibility of the plasma-assisted shrink technique was evaluated through extensive SEM inspections after lithography, after shrink, and after etch, as well as through electrical evaluations.


Proceedings of SPIE | 2008

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Janko Versluijs; J.-F. de Marneffe; Danny Goossens; Maaike Op de Beeck; Tom Vandeweyer; Vincent Wiaux; H. Struyf; Mireille Maenhoudt; Mohand Brouri; Johan Vertommen; Jisoo Kim; Helen Zhu; Reza Sadjadi

Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the MotifTM CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.


Plasma Sources Science and Technology | 2006

Plasma ignition in a grounded chamber connected to a capacitive discharge

M. A. Lieberman; A. J. Lichtenberg; Sungjin Kim; Jon Tomas Gudmundsson; Douglas Keil; Jisoo Kim

A capacitive discharge connected through a dielectric or metal slot to a peripheral grounded region is a configuration of both theoretical and practical interest. The configuration is used in commercial dual frequency capacitive discharges, where a dielectric slot surrounding the substrate separates the main plasma from the peripheral grounded pumping region. Ignition of the peripheral plasma produces effects such as poor matching and relaxation oscillations that are detrimental to processing performance. Discharge models are developed for diffusion and plasma maintenance in the slot, and plasma maintenance in the periphery. The theoretical predictions of ignition conditions as a function of voltage and pressure are compared with experimental results for a driving frequency of 27.12 MHz and a gap spacing of 0.635 cm connecting the two regions, giving good agreement.


Journal of Micro-nanolithography Mems and Moems | 2009

30-nm half-pitch metal patterning using Motif™ critical dimension shrink technique and double patterning

J. Versluijs; Jean-Francois de Marneffe; Danny Goossens; T. Vandeweyer; Vincent Wiaux; Herbert Struyf; Mireille Maenhoudt; Mohand Brouri; Johan Vertommen; Jisoo Kim; Helen Zhu; Reza Sadjadi

Double-patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double-patterning process is discussed for 30-nm half-pitch interconnect structures, using 1.2 numerical aperture immersion lithography combined with the MotifTM critical dimension (CD) shrink technique. An adjusted optical proximity correction (OPC) calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography-based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30-nm half-pitch pattern into the MHM.


international symposium on semiconductor manufacturing | 2007

Novel patterning shrink technique enabling sub-50 nm trench and contact integration

Steven Demuynck; Zsolt Tokei; Chao Zhao; J.-F. de Marneffe; Herbert Struyf; Werner Boullart; M.O. de Beeck; L. Carbonell; Nancy Heylen; J. Vaes; Gerald Beyer; S. Vanhaelemeersch; Reza Sadjadi; Helen Zhu; Peter Cirigliano; Jisoo Kim; Johan Vertommen; B. Coenegrachts; Elizabeth Pavel; Amulya Athayde

In this paper we demonstrate the feasibility of integrating a technique for shrinking the lithography-defined feature size by using a plasma process prior to etch. The technique is based on a sequential deposition and selective removal of a polymer coating formed on the top and sidewalls of the developed resist. This method can be applied to both contacts and trenches and allows tuning of the shrink amount. Yielding damascene trenches down to 45 nm were obtained, shrunk from a 85 nm print, while functional 100 nm contacts were formed starting from a 150 nm print. In both cases excellent within-wafer non-uniformities were achieved.


Archive | 2008

PITCH REDUCTION USING OXIDE SPACER

Jisoo Kim; Conan Chiang; Jun Shinagawa; S. M. Reza Sadjadi


Archive | 2006

Self-aligned pitch reduction

Jisoo Kim; Sangheon Lee; Daehan Choi; S. M. Reza Sadjadi

Collaboration


Dive into the Jisoo Kim's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge