Reza Sadjadi

A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond

Limits to the lithography process window restrict the scaling of critical IC features such as holes (contact, via) and trenches (required for interconnects and double patterning applications). To overcome this problem, contacts or trenches can be oversized during the exposure, followed by the application of a shrink technique. In this work, a novel shrink process utilizing plasma-assisted polymer deposition is demonstrated: a polymer is deposited on the top and sidewalls of photoresist by alternating deposition and etch steps, reducing the dimension of the lithography pattern in a controlled way. Hence very small patterns can be defined with wide process latitudes. This approach is generic and has been applied to both contacts and trenches. The feasibility of the plasma-assisted shrink technique was evaluated through extensive SEM inspections after lithography, after shrink, and after etch, as well as through electrical evaluations.

E-beam curing effects on the etch and CD-SEM stability of 193-nm resists

Electron beam (e-beam) curing techniques are known to improve etch and CD-SEM stability of 248 and 193nm resists. The effects of three different e-beam curing processes (standard, LT and ESC) on the methacrylate and hybrid type 193nm resists were studied with respect to resin chemistry changes, resist film shrinkage, pattern profiles, etch rates, and CD SEM stability. Both methacrylate and hybrid type 193nm resists lose carbonyl groups from the resins, with possibly a reduction in the free volume leading to improved etch resistance/selectivity. Methacrylate resist films shrink ca. 22-24% and hybrid resist films shrink ca. 23-27%. The LT process shrinks the least compared to the ESC and standard process. The ESC and LT processes were found to stabilize the patterns uniformly compared to the standard process. Etch rate, selectivity and resist surface roughness after etch of both methacrylate and hybrid resists were improved using the e-beam curing process. E-beam curing drastically reduces the CD SEM shrinkage (from ca. 15% to 2- 5%); however, considerable shrinkage occurs during the curing process itself.

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Double patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double patterning process is discussed for 30nm half-pitch interconnect structures, using 1.2 NA immersion lithography combined with the MotifTM CD shrink technique. An adjusted OPC calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30nm half-pitch pattern into the MHM.

30-nm half-pitch metal patterning using Motif™ critical dimension shrink technique and double patterning

Double-patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double-patterning process is discussed for 30-nm half-pitch interconnect structures, using 1.2 numerical aperture immersion lithography combined with the MotifTM critical dimension (CD) shrink technique. An adjusted optical proximity correction (OPC) calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography-based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30-nm half-pitch pattern into the MHM.

Novel patterning shrink technique enabling sub-50 nm trench and contact integration

In this paper we demonstrate the feasibility of integrating a technique for shrinking the lithography-defined feature size by using a plasma process prior to etch. The technique is based on a sequential deposition and selective removal of a polymer coating formed on the top and sidewalls of the developed resist. This method can be applied to both contacts and trenches and allows tuning of the shrink amount. Yielding damascene trenches down to 45 nm were obtained, shrunk from a 85 nm print, while functional 100 nm contacts were formed starting from a 150 nm print. In both cases excellent within-wafer non-uniformities were achieved.

Plasma-assisted CD shrink and overlay metrology techniques for double patterning

Double patterning lithography is being considered for semiconductor manufacturing at the 32 nm technology node. In the double exposure approach, double patterning is accomplished with two cycles of lithography and etch. A tight overlay tolerance is required to prevent registration errors between the lithography steps from transferring as CD errors in the final pattern. Here we present a double patterning scheme with a novel plasma-assisted CD shrink technique to reduce the feature size after each lithography exposure, providing both pitch and CD shrink. Scatterometry-based metrology is shown to be able to detect registration errors down to 1 nm.

Organic Offset Deposition by Innovative Plasma Technology: Channel Length Modulation for NOR Flash Memories

Self-Aligned-Source (SAS) technology is a process option commonly used in process integration for Flash NOR. This approach is realized by removing the field oxide from the source lines of the array, which is implanted with N-type dopant, so two adjacent word lines can be fully driven by the same source contact. Since field oxide removal is demanded to a RIE, a polymer layer on cell sidewall is expected after this step. The presence of this thin organic layer during the subsequent implantation step is supposed to act as a spacer, hence modulating the effective channel length (Leff). According to the continuous shrink of memory cell, this spacer becomes relevant compared with cell dimension and can not be neglected as second order effect. It is known that polymer deposition during etching step is not a perfectly controllable phenomenon. As a consequence, fluctuations in polymer thickness yield to fluctuations in cell characteristics. So, poor run-to-run, intra-wafer and even intra-sector repeatabilities often are the results. TEM analysis and electrical validations have been reported to demonstrate the relationships between deposited polymer presence and cell parameters spread. Figure 1 below is an example of TEM data.