Jiun-Jia Huang

Bipolar Nonlinear

A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO2/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO2 barriers. The series connection with an HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.

\hbox{Ni/TiO}_{2}\hbox{/}\hbox{Ni}

Lack of a suitable selection device to suppress sneak current has impeded the development of 4F2 crossbar memory array utilizing stable and scalable bipolar resistive-switching. We report a high-performance nonlinear bipolar selector realized by a simple Ni/TiO2/Ni MIM structure with a high current density of 105 A/cm2, and a Ni/TiO2/Ni/HfO2/Pt vertically stacked 1S1R cell capable of gigabit memory implementation. Furthermore, the demonstration of 1S1R array fabricated completely at room temperature on a plastic substrate highlights the promise of future extremely low-cost flexible nonvolatile memory.

Selector for 1S1R Crossbar Array Applications

This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector-one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonnegligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed.

One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications

In this letter, a polycrystalline silicon thin-film transistor (poly-Si TFT) with high-quality praseodymium oxide (Pr2O3) gate dielectric is proposed. Compared to TFTs with tetraethoxysilane gate dielectric, the electrical characteristics of poly-Si TFTs with Pr2O3 gate dielectric can be significantly improved, such as lower threshold voltage, lower subthreshold swing, triple ON/OFF current ratio, and a field-effect mobility that is about twice higher, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density by using a high-kappa gate dielectric. Therefore, the poly-Si TFT with Pr2O3 high-kappa gate dielectric is a promising candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

Dependence of Read Margin on Pull-Up Schemes in High-Density One Selector–One Resistor Crossbar Array

A comprehensive study of SET speed-disturb dilemma in resistive-switching random access memory (RRAM) is presented using statistically based prediction methodologies, accounting for the stochastic nature of SET. An analytical percolation model has been successful in explaining the statistical Weibull distribution of SET time and SET voltage in addition to the power-law voltage-time dependence. Two prediction methodologies using constant voltage stress (CVS) and ramp voltage stress (RVS) are proposed to evaluate the SET speed-disturb properties. The RVS method reduces analysis time and cost and yields equivalent results as the CVS method. Furthermore, the RVS method is used to evaluate the device design space and the current status of RRAM technology to meet the strict requirement of the SET speed-disturb dilemma.

High-Performance Poly-Si TFTs With

GaN (gallium nitride)-based light-emitting diodes (LEDs) with a nano-scale SiO2 structure between a transparent indium-tin oxide (ITO) layer and p-GaN were fabricated. The forward voltage at 20 mA for a GaN-based LED with a SiO2 nano-scale structure was slightly higher than that of a conventional GaN-based LED because the total area of the p-type metal contact between the transparent ITO layer and p-GaN was smaller. However, the light output power for the GaN-based LED with a nano-scale structured SiO2 at 20 mA was 24% higher than that for a conventional GaN-based LED structure. This increase in the light output power is mostly attributed to the scattering of light from the SiO2 photonic quasi-crystal (PQC) layer.

\hbox{Pr}_{2} \hbox{O}_{3}

We report the first demonstration of a flexible one diode–one resistor (1D1R) resistive-switching (RS) memory cell capable of high-density crossbar array implementation at an extremely low cost. A Ti/TiO2/Pt diode with a large rectifying ratio and a stable Ni/HfO2/Pt unipolar RS memory element have been fabricated on a polyimide substrate using only room-temperature processes. No significant degradation of the rectifying ratio of the TiO2 diode and the cycling variations, retention, and read disturb immunity of the HfO2 memory was observed in the bending state. The series 1D1R cell shows highly reproducible unipolar RS because of the low reset current of the HfO2 memory, which greatly mitigates the adverse effect of diode series resistance. Furthermore, the 1D1R cell can effectively suppress read interference and realize a crossbar array as large as 512 kbit.

Gate Dielectric

This letter proposes a novel technique for predicting with high confidence the disturbance of the resistive-switching random access memory (RRAM) RESET state based on ramped voltage stress. The technique yields statistical distributions and voltage acceleration parameters equivalent to those of a conventional constant voltage method. Several ramp rates and acceleration models were validated for the accuracy regarding conversion between the two methods. The proposed method not only reduces the time and cost of reliability analysis but also provides a quantitative link between disturbance properties and the widely available RRAM data measured by a linear voltage ramp. Additionally, the non-Poisson area scaling supports the localized filament model.

Statistical Model and Rapid Prediction of RRAM SET Speed–Disturb Dilemma

The enhancement of light extraction from GaN-based light-emitting diodes (LEDs) with a patterned sapphire substrate (PSS) and a SiO2 12-fold photonic quasi-crystal (PQC) structure using nanoimprint lithography is presented. At a driving current of 20 mA on transistor-outline-can package, the light output powers of LED with a PSS and LED with a PSS and a SiO2 PQC structure are enhanced by 35% and 48%, compared with the conventional LED. In addition, the higher output power of the LED with a PSS and a SiO2 PQC structure is due to better reflectance on PSS and higher epitaxial quality on an n-GaN using a SiO2 12-fold PQC structure pattern. These results provide promising potential to increase output powers of commercial light-emitting devices.

Enhancement of light output power of GaN-based light-emitting diodes using a SiO(2) nano-scale structure on a p-GaN surface

This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.