Chih-Kang Deng

High-Performance Poly-Si TFTs With

In this letter, a polycrystalline silicon thin-film transistor (poly-Si TFT) with high-quality praseodymium oxide (Pr2O3) gate dielectric is proposed. Compared to TFTs with tetraethoxysilane gate dielectric, the electrical characteristics of poly-Si TFTs with Pr2O3 gate dielectric can be significantly improved, such as lower threshold voltage, lower subthreshold swing, triple ON/OFF current ratio, and a field-effect mobility that is about twice higher, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density by using a high-kappa gate dielectric. Therefore, the poly-Si TFT with Pr2O3 high-kappa gate dielectric is a promising candidate for high-speed and low-power display driving circuit applications in flat-panel displays.

\hbox{Pr}_{2} \hbox{O}_{3}

To overcome the offset voltage (VOS) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-mum LTPS technology. Using the offset compensation technique, the VOS of output buffer can be controlled within plusmn100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel

Gate Dielectric

High-performance polycrystalline silicon thin-film transistors (poly-Si TFTs) integrating high-K Pr 2 O 3 gate dielectric and fluorine-passivated poly-Si film are demonstrated. High gate capacitance density and thin equivalent-oxide thickness provided by the high-K Pr 2 O 3 gate dielectric have the advantage of increasing the driving current capability of the TFT device, but an undesirable off-state leakage current could be introduced from the high electric field near the drain side. Introducing fluorine atoms into poly-Si films by employing a low-temperature CF 4 plasma treatment can effectively passivate the trap states. With 10 W CF 4 plasma treatment on poly-Si film, the electrical characteristics of poly-Si Pr 2 O 4 TFTs can be significantly improved, including a steeper subthreshold swing, smaller threshold voltage, higher field-effect mobility, and better on/off current ratio compared with that without CF 4 plasma treatment. The maximum off-state leakage current of the fluorine-passivated TFT is more than one order of magnitude lower than that of the control TFT. Furthermore, the incorporation of fluorine atoms by CF 4 plasma treatment also improves the reliability of poly-Si Pr 2 O 3 TFTs against hot carrier stressing, which is due to the formation of stronger Si-F bonds in place of weak Si-H bonds in the poly-Si channel and at the Pr 2 O 3 gate dielectric/poly-Si interface. Therefore, high-performance and high-reliability poly-Si TFTs with Pr 2 O 3 gate dielectric and CF 4 plasma treatment on poly-Si film are suitable for active-matrix liquid crystal display application.

On-panel output buffer with offset compensation technique for data driver in LTPS technology

High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-scale feature sizes can be easily fabricated, exhibiting superior channel controllability through the triple-gate structure. In employing the MILC technique, the grain crystallinity of NW channels is significantly superior to that formed by the solid-phase-crystallization (SPC) technique. Therefore, the MILC NW TFT exhibits greatly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, and higher field-effect mobility, as compared to those of the SPC NW TFT. Moreover, the superior threshold-voltage rolloff characteristics of MILC NW TFT are also demonstrated.

CF4-Plasma-Induced Fluorine Passivation Effects on Poly-Si TFTs with High- κ Pr2O3 Gate Dielectric

A class-B output buffer with threshold voltage (VTH) compensation for the data driver circuit fabricated on liquid crystal display (LCD) panel in low temperature polysilicon (LTPS) technology is proposed. This output buffer can be operated at 50-kHz operation frequency with a 2-to-8 V output swing for extended graphic array (XGA) application. By employing the design technique of threshold voltage compensation, the offset voltage (VOS) of the class-B output buffer under 2-to-8 V input signal can be controlled within ±100 mV for a high resolution and quality applications in LCD panel.

High-Performance Nanowire TFTs With Metal-Induced Lateral Crystallized Poly-Si Channels

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k Pr₂O₃ as gate dielectric is investigated for the first time. Using the Pr₂O₃ gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr₂O₃/poly-Si interface to improve the device electrical properties. The Pr₂O₃ TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr₂O₃ TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr₂O₃ TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr₂O₃ TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.

P‐17: On‐Panel Design Technique of Threshold Voltage Compensation for Output Buffer in LTPS Technology

The electrostatic discharge (ESD) robustness of different thin-film devices, including three diodes and two thin-film transistors (TFTs) in low-temperature polysilicon (LTPS) technology, is investigated. By using the transmission line pulse generator (TLPG), the high-current characteristics and the secondary breakdown current (It2) of these thin-film devices are observed. The experimental results with different parameters and layout structures of these LTPS thin-film devices have been evaluated for optimizing ESD protection design for liquid crystal display (LCD) panel.

Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With

In this study, we demonstrate the stability of highLa2O3 metal–insulator–metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance ( ) decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of . Additionally, high stability of 10-year lifetime is achieved for a 10-nm La2O3 MIM capacitor with an 11.4 fF/mm capacitance density. # 2010 The Japan Society of Applied Physics