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Dive into the research topics where Joachim Krumrey is active.

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Featured researches published by Joachim Krumrey.


Microelectronics Reliability | 2007

A novel SIMS based approach to the characterization of the channel doping profile of a trench MOSFET

Rudolf Zelsacher; Andrew Wood; E. Bacher; E. Prax; K. Sorschag; Joachim Krumrey; J. Baumgartl

We present here a new technique which for allows the accurate characterization of the channel doping profile using secondary ion mass spectrometry (SIMS) analysis within the active area cells of a trench MOSFET. The technique involves the chemical removal of the entire structure apart from the silicon mesas and trenches, followed by the deposition of undoped silicon (polycrystalline or epitaxial) to refill the trenches. The SIMS profiles obtained are then corrected for the trench geometry to reveal the underlying doping profile within the MOSFET cells.


Archive | 2004

Simulation of the failure mechanism of power DMOS transistors under avalanche stress

A. Icaza Deckelmann; G. Wachutka; Joachim Krumrey; Franz Hirler

The failure mechanism caused by avalanche stress in power devices consisting of large DMOS cell arrays is investigated using electrothermal device simulation. To this end, we use the approximation of an infinitely large array, but allow for thermal interaction among the cells. The numerical analysis demonstrate the occurrence of unstable states, where a single hot spot and a current filament evolve in one particular ‘weak’ cell, thus confirming earlier work. We also demonstrate that the maximum temperature rise in the first cell exhibiting filamentary current flow can easily exceed the destructive level. Subsequent current and temperature redistributions observed in simulation thus turn out to be of no practical relevance.


Archive | 2003

Method for fabricating a transistor configuration including trench transistor cells having a field electrode, trench transistor, and trench configuration

Ralf Henninger; Franz Hirler; Joachim Krumrey; Walter Rieger; Martin Pölzl; Heimo Hofer


Archive | 2003

Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitance

Ralf Henninger; Franz Hirler; Joachim Krumrey; Walter Rieger; Martin Poelzl


Archive | 2003

Semiconductor component with an increased breakdown voltage in the edge area

Ralf Henninger; Franz Hirler; Joachim Krumrey; Markus Zundel; Walter Rieger; Martin Pölzl


Archive | 2002

Semiconductor arrangement with a MOS-transistor and a parallel Schottky-diode

Wolfgang Werner; Franz Hirler; Joachim Krumrey; Walter Rieger


Archive | 2003

Transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell

Joachim Krumrey; Franz Hirler; Ralf Henninger; Martin Pölzl; Walter Rieger


Archive | 2011

MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING

Oliver Haeberlen; Walter Rieger; Lutz Goergens; Martin Poelzl; Johannes Schoiswohl; Joachim Krumrey


Archive | 2002

Verfahren zur Herstellung einer Transistoranordnung mit Trench-Transistorzellen mit Feldelektrode

Ralf Henninger; Franz Hirler; Joachim Krumrey; Walter Rieger; Martin Poelzl; Heimo Hofer


Archive | 2002

Production of a transistor arrangement comprises inserting a trench in a process layer of a semiconductor substrate, and forming a drift zone, a channel zone and a source zone in the process zone

Ralf Henninger; Franz Hirler; Joachim Krumrey; Walter Rieger; Martin Poelzl; Heimo Hofer

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