Joakim Hallin

A 165-Gb/s 4:1 multiplexer in InP DHBT technology

This paper presents a 4:1 multiplexer fabricated in InP DHBT technology. The multiplexer works up to 165 Gb/s. At 165 Gb/s, the chip operates at -3.2 V supply voltage and consumes 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenges were timing margins between clock and data.

Thermal phase transition in weakly interacting, large NC QCD

Abstract We consider thermal QCD in the large NC limit, mainly in 1+1 dimensions. The gauge coupling is only taken into account to minimal order, by projection onto colour singlets. An expression for the free energy, exact as NC→∞, is then obtained. A third order phase transition will occur. The critical temperature depends on the ratio NC/L, where L is the (infinite) spatial length. In the high temperature limit, the free energy will approach the same value as in the free theory, whereas we have a mesonic like phase at low temperature. Expressions for the quark condensate, 〈 Ψ Ψ〉 , are also obtained.

A 100-Gb/s 1:4 Demultiplexer in InP DHBT Technology

This paper presents a 1:4 demultiplexer fabricated in InP DHBT technology. The demultiplexer is verified to work up to 100 Gb/s at a supply voltage of -3.6 V consuming 2.1 W. It is a half-rate demultiplexer using multi-phase clock architecture. To verify operation up to 100 Gb/s the authors used an in-house PRBS generator chip

104Gb/s 2"-1 and 110Gb/s 2-1 PRBS Generator in InP HBT Technology

A 211-1 PRBS generator with one output at a maximum data rate of 104Gb/s and 4 parallel outputs at 52Gb/s is presented together with a 29-1 PRBS generator with a single output at 110Gb/s. The ICs are implemented in a 300GHz fT InP HBT technology. The generator core is clocked at half the data rate of the high-speed output for both circuits. They dissipate 2.8W and 2.2W from a -3.5V supply, respectively

Design and Test of InP DHBT ICs for a 100 Gb/s Demonstrator System

We report on design and test of state-of-the-art building blocks for a 100 Gb/s demonstrator system: a 165 Gb/s 4:1 multiplexer IC and a 110 Gb/s PRBS generator IC in InP DHBT technology.

Representations of the SU(N) T-algebra and the loop representation in 1 + 1 dimensions

We consider the Yang--Mills phase space on a cylindrical spacetime () and the associated algebra of gauge-invariant functions, the T-variables. We solve the Mandelstam identities both classically and quantum mechanically by considering the T-variables as functions of the eigenvalues of the holonomy and their associated momenta. It is shown that there are two inequivalent representations of the quantum T-algebra. Then we compare this reduced phase-space approach to Dirac quantization and find it gives essentially equivalent results. We proceed to define a loop representation in each of these two cases. One of these loop representations (for N=2) is more or less equivalent to the usual loop representation.

Explicit gauge-invariant quantization of the Schwinger model on a circle in the functional Schrödinger representation.

We solve the Schwinger model on a circle by first finding the explicit ground state functional(s). Having done this, we give the structure of the Hilbert space and derive bosonization formulas in this formalism. {copyright} {ital 1996 The American Physical Society.}

Flip-chip mounted 1:4 demultiplexer IC in InP DHBT technology operating up to 100 Gb/s

Operation of a packaged 1:4 demultiplexer (DEMUX) in InP DHBT technology for an input data rate of up to 100 Gb/s is presented. The DEMUX IC is flip-chip mounted in a microwave package consisting of an aluminum nitride substrate with coplanar waveguides placed in a Kovar/MoCu housing with coaxial V-connectors. The DEMUX was operated at a supply voltage of -3.5 V and consumes 2.1 W.

94-Gb/s 29-1 PRBS Bit Error Detector IC in InP DHBT Technology

In this paper, the authors present a bit-error detector IC for 2 9 - l PRBS signals. The IC is fabricated in InP DHBT technology and operates for input data rates up to a record high 94 Gb/s. Each detected bit-error on the input signal produces a logic transition on the output signal. The IC consumes 1.5 W from a -2.5 V supply voltage