Joaquín Alvarado

Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology Roadmap of Semiconductors projection, it is mandatory to find layout or technological solutions to reduce the total parasitic gate capacitance. In this context, it is necessary to develop a model that describes the parasitic capacitance in terms of the FinFET geometry. In this paper, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3-D numerical simulations, is presented. The model takes into account the external (five components) and internal (two components) fringing capacitances from the gate to the source/drain electrodes as well as the overlap capacitances. Comparisons with experimental results are presented to validate the developed model. Finally, based on the developed model, the evolution of the total parasitic gate capacitance as the channel length is reduced toward the 12-nm technology node is analyzed.

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs

This paper presents a compact model for partially depleted SOI MOSFETs, which allows for describing the total dose and the single event effects. It incorporates both temperature and charge buildup effects during irradiation. The developed model is implemented in a Verilog-A module. This original module can be coupled with Spice simulator, allowing for faster (time efficient) circuit simulations (comparing to numerical physical ones) at different bias, linear energy transfer (LET), buildup charges and temperatures. Better efficiency and flexibility than the standard current source method is achieved thanks to the direct link between the module and the irradiated transistor through the partially depleted SOI CMOS body contact terminal. Mixed-mode simulations of a partially depleted SOICMOS D flip-flop at different conditions (biases, LETs, temperatures, buildup charge densities) are used in order to validate the model. Well-known high tolerance of SOI circuits to a single event effects is demonstrated to be degraded with the total dose increase (appearing as a positive charge buildup), which is further enhanced at higher temperatures

Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors

The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. In this paper we show the advantages of using the recently developed Symmetric Doped Double-Gate Model as already introduced in SmartSpice simulator, for modeling circuits containing Double-Gate Graded-Channel (GC) transistors. In this case there is no need to use two different models to represent the graded-channel device, as has been done up to now. Current-mirror circuits using GC devices have been simulated and the results were validated comparing them with those obtained using the MIXED-MODE module of two-dimensional numerical ATLAS simulator of the GC devices.

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V/sub th/ deep-submicrometer 0.12-/spl mu/m silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25/spl deg/C-220/spl deg/C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.

Automatic parameter extraction techniques in IC-CAP for a compact double gate MOSFET model

In this paper, automatic parameter extraction techniques of Agilents IC-CAP modeling package are presented to extract our explicit compact model parameters. This model is developed based on a surface potential model and coded in Verilog-A. The model has been adapted to Trigate MOSFETs, includes short channel effects (SCEs) and allows accurate simulations of the device characteristics. The parameter extraction routines provide an effective way to extract the model parameters. The techniques minimize the discrepancy and error between the simulation results and the available experimental data for more accurate parameter values and reliable circuit simulation. Behavior of the second derivative of the drain current is also verified and proves to be accurate and continuous through the different operating regimes. The results show good agreement with measured transistor characteristics under different conditions and through all operating regimes.

Efficient single event upset simulations of a tolerant PD SOI CMOS D Flip-Flop

A simple way for modeling the single event upset (SEU) in Partially Depleted (PD) SOI CMOS circuits by Spice simulations is presented. A Verilog-A module connected to the body contact of PD SOI MOSFET is implemented to describe the transient current generated by an ion-track crossing the transistor. Verilog-A module is given by a physical based compact model and hence accounts for all variations in MOSFETs physical parameters (i.e. mobility, lifetime, etc.) caused by irradiation, temperature, bias conditions, etc. Good agreement with mixed-mode numerical simulations is observed at different conditions. Both kinds of simulations show that PD SOI CMOS D Flip-Flop is tolerant to high LET energies, whereas bias supply reduction as well as an increase in the clock frequency of the flip-flop can degrade this tolerance.

Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models

In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. Template devices representative for a downscaled symmetric double-gate MOSFET was used to validate the models for n-channel and p-channel. A CMOS inverter and a ring oscillator have been analyzed. Comparison of its performance between the drift-diffusion (DD) and hydrodynamic transport model within the practical range of bias voltages has been highlighted.

Impact of neutron irradiation on oxidized high-resistivity silicon substrates with and without a trap-rich passivation layer

This work investigates the influence of high-energy neutrons on oxidized high-resistivity Si substrates. Two oxide thicknesses as well as the presence of a trap-rich passivation layer are considered. The impact of neutron irradiation is directly related to the competition between the generation of interface traps, which are beneficial to reduce parasitic surface conduction (PCS) into the Si substrate similarly to the passivation layer, and accumulation of radiation induced positive charges in oxide, which would unfortunately increase PSC. It is shown that under neutron irradiation, RF losses are strongly reduced in the case of thin oxide, while substrates with a polysilicon passivation layer are almost insensitive to the neutron irradiation.

Verilog - A Implementation of ICS Model for PD SOI Devices

We present a Verilog-A implementation of an Improved Charge Sheet Model (ICSM) for PD SOI MOSFETs. This model is a physical and continuous compact model for deep-submicron transistors focused in an accurate description of high order derivatives, in order to obtain good approximation of the harmonic distortion behavior. The implementation of the model, using Verilog-A language, allows analog circuit designer simulate their PD SOI design in SPICE circuit simulators, expecting reliable results.

Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

A physically based model of the double-gate juntionless transistor which is capable of describing accumulation and depletion regions is implemented in Verilog-A in order to perform DC circuit simulations. Analytical description of the difference of potentials between the center and the surface of the silicon layer allows the determination of the mobile charges. Furthermore, mobility degradation, series resistance, as well as threshold voltage roll-off, drain saturation voltage, channel shortening and velocity saturation are also considered. In order to provide this model to all of the community, the implementation of this model is performed in Ngspice, which is a free circuit simulation with an ADMS interface to integrate Verilog-A models. Validation of the model implementation is done through 2D numerical simulations of transistors with and silicon channel length and 1 × 1019 or doping concentration of the silicon layer with 10 and silicon thickness. Good agreement between the numerical simulated behavior and model implementation is obtained, where only eight model parameters are used.