V. Kilchytska

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFETs with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs

This paper investigates the influence of the silicon substrate on the ac characteristics of silicon-on-insulator (SOI) MOSFETs. It is shown for the first time that the presence of the substrate underneath the buried oxide results in two transitions (i.e., zero-pole doublets) in the frequency response of the output conductance. It is demonstrated that the appearance of these transitions, the position and amplitude of which strongly depend on the substrate doping, is caused by the variation of the potential at substrate-buried oxide interface, which we call the Floating Effective Back-Gate (FEBG) effect. A first-order small-signal equivalent circuit is proposed to support our observations.

On the high-temperature subthreshold slope of thin-film SOI MOSFETs

This paper addresses the validity of the classical expression for the subthreshold swing (S) in SOI metal-oxide semiconductor field effect transistors (MOSFETs) at high temperature. Using numerical simulation, it is shown that two effects invalidate the classical expression of S at high temperature. Firstly, the depletion approximation becomes invalid and intrinsic free carriers must be taken into account to determine the effective body capacitance. Secondly, the charge-sheet model for the inversion layer becomes inaccurate due to a lowering of the electric field at the surface and a broadening of the inversion layer thickness in weak inversion. These effects must be taken into account to predict accurately the high-temperature subthreshold characteristics of both partially depleted and fully depleted SOI MOSFETs.

Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk

Frequency variation of the output conductance in advanced fully depleted SOI and multiple-gate MOSFETs related to the electrical coupling between drain and Si substrate underneath the buried oxide (BOX) is analyzed through measurements and 2-D simulations. A low-frequency (LF) conductance variation in these devices, which could be erroneously attributed to the self-heating effect, is proved to be related to the presence of the Si substrate underneath the BOX. Suppression of this substrate-related LF transition in narrow-fin FinFETs output conductance is experimentally demonstrated. Furthermore, the substrate-related transitions are shown to be increasing with device downscaling, as well as BOX thinning, suggesting that this effect becomes more important for the future device generations

Compact model for single event transients and total dose effects at high temperatures for partially depleted SOI MOSFETs

This paper presents a compact model for partially depleted SOI MOSFETs, which allows for describing the total dose and the single event effects. It incorporates both temperature and charge buildup effects during irradiation. The developed model is implemented in a Verilog-A module. This original module can be coupled with Spice simulator, allowing for faster (time efficient) circuit simulations (comparing to numerical physical ones) at different bias, linear energy transfer (LET), buildup charges and temperatures. Better efficiency and flexibility than the standard current source method is achieved thanks to the direct link between the module and the irradiated transistor through the partially depleted SOI CMOS body contact terminal. Mixed-mode simulations of a partially depleted SOICMOS D flip-flop at different conditions (biases, LETs, temperatures, buildup charge densities) are used in order to validate the model. Well-known high tolerance of SOI circuits to a single event effects is demonstrated to be degraded with the total dose increase (appearing as a positive charge buildup), which is further enhanced at higher temperatures

Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs

It is generally recognized that very narrow silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) are insensitive to substrate bias due to the strong electrostatic gate control. In this letter, we demonstrate, for the first time, that, in short-channel narrow FinFETs, substrate bias can dramatically change the on-current without change in the threshold voltage, subthreshold slope, and drain-induced barrier lowering, due to the modulation of the parasitic series resistance. Therefrom, contrary to general belief, very narrow short-channel multiple-gate field-effect transistors can be sensitive to substrate-related effects (buried oxide formation, irradiation, etc). Another important implication of the described effect is related to the diagnostics of the series resistance in SOI FinFETs and better prediction of their full intrinsic performance potential.

Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications

This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance g m , the output conductance g d , the intrinsic gain A v and the cut-off frequencies f t and f max . Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, g m -A v analogue metrics is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that f t reaches ∼270 GHz in the shortest devices.

On the UTBB SOI MOSFET performance improvement in quasi-double-gate regime

This work investigates the simultaneous electrostatic improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing gate and substrate (or ground plane) as Vsub=k*Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. QDG mode is demonstrated to allow threshold voltage tuning and on-current enhancement without off-state current degradation, of interest for digital applications (e.g. switches). Improved performance in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. The work finally quantifies the resulting gate area decrease in QDG mode, potentially exploitable in actual circuit implementations.

Substrate Effect on the output conductance frequency response of SOI MOSFETs

The paper analyzes the influence of the Si substrate on the AC characteristics of silicon-on-insulator (SOI) MOSFETs through 2D Atlas simulations and measurements. It is shown that the presence of the Si substrate underneath the buried oxide (BOX) results in two transitions in the frequency response of the output conductance, caused by the variation of the potential at substrate-BOX interface. A first-order small-signal model is proposed to support the obtained results. It is demonstrated that the appearance of “substrate-related” transitions, their position and amplitude depend strongly on the substrate doping, space-charge conditions at substrate-BOX interface, temperature and moreover become more pronounced with device downscaling.

Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V/sub th/ deep-submicrometer 0.12-/spl mu/m silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25/spl deg/C-220/spl deg/C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.