Nils Heidmann

The intelligent container as a part of the Internet of Things

Perishables need special conditions within the food supply chain like temperature or humidity. There is a lack of information along the food supply chain (FSC) concerning temperatures for perishable goods. By integrating the Intelligent Container (IC) within the Internet of Things the lack of information will be eliminated and thus wastes of food will be reduced. The first step for this integration is to analyze common techniques in modeling supply chains and especially the FSC and create a model taking into consideration the concept of the IC. On this basis, technologies to generate information along the FSC are shown and the IC is linked to the Internet of Things. Finally, a logistic reference model will be deduced from the Internet of Things for perishables.

Architecture and FPGA-implementation of a high throughput K + -Best detector

Since Multiple Input Multiple Output (MIMO) transmission has become more and more popular for current and future mobile communication systems, MIMO detection is a big issue. Linear detection algorithms are less complex and well understood but their BER performance is limited. ML detectors achieve the optimum result but have exponential computational complexity. Hence, iterative tree-search algorithms like the sphere decoder or the K-Best detector, which reduce the computational complexity, has become a major topic in research. In this paper a modified K+-Best detector is introduced which is able to achieve the BER performance of a common K-Best detector with K=12, by using a sorting algorithm for K=8. This novel sorting approach based on Batchers Odd-Even Mergesort is less complex compared to other parallel sorting designs and saves valuable hardware resources. Due to an efficient implementation the throughput of the detector is about 455 Mbit/s which is twice as high as the LTE peak data rate of 217.6 Mbit/s for a 16-QAM modulated signal. In this paper the architecture and the implementation issues are demonstrated in detail and the BER performance of the K+-Best FPGA implementation is shown.

Modeling of an analog recording system design for ECoG and AP signals

The recording of neural activities has turned out to be a promising approach to understand the basic function of specific brain parts like the visual or motor cortex. However, the development and design of advanced neural recording systems is very challenging since the number of parallel measurement channels increases continuously. Beside the analog recording channels digital preprocessing becomes mandatory to handle the corresponding amount of data and to adapt this data to the available transmission bandwidth. In this paper we present the design as well as the behavioral modeling of an analog recording front-end. Simulation and measurement results demonstrate the performances of the system for recording neural signals. Since simulation of this analog front-end is very time consuming but essential for large fully-integrated designs, a mixed-signal model approach is introduced that enables a significant simulation acceleration of integrated and external analog front-ends. The simulation can be accelerated by a factor of up to 22.2 for a single front-end. The proposed system has been fabricated in a 0.35 μm CMOS technology and performances have been measured. This demonstrates that the behavioral model is compatible to the transistor level design. A neural spike detector shows the transient performance of the modeled design on real input stimuli.

AAS-Maps: Aging-aware sensitivity-maps for reliability driven analog circuit design

Analog design is facing new challenges as reliability requirements are increasingly moving into focus for target specifications. Methods providing a degradation-aware design flow exist, but mostly involve algorithmic optimization and lack of computational efficiency and circuit insight. This paper proposes the use of aging-aware sensitivity maps generated by operating point-dependent degradation within the gm/Id scheme. Sensitivity values proof to be a good measure for circuit degradation. Different designs of a common source amplifier structure are investigated by comparing aging sensitivities and simulated degradation. The results show that in opposition to existing methods this technique enables aging-aware design during design phase with comparatively low computational effort.

Using operating point-dependent degradation and g m /I D method for aging-aware design

Effects like NBTI and HCI are degrading the characteristics of analog circuits. Available countermeasures to maintain system performances often include the use of optimizers or other external tools to size devices appropriately, which give no insight in relations between degradation and circuit parameters for the designer. This paper proposes an extension of the gm/ID sizing method by considering aged transistor parameters for fresh circuit design. A possible usage scenario for this investigation is given by optimizing a simple circuit towards higher reliability. The degradation in amplification of a common source amplifier is reduced by 19 % for a full time operation of 10 years.

Optimum Operating Points of Transistors with minimal Aging-Aware Sensitivity

Degradation of the threshold voltage in CMOS transistors affects the performance of analog circuits over time. In order to meet set target specifications, the influence of these degradation modes needs to be considered and compensated during the design phase. This work introduces an aging-aware sensitivity function, which allows the computation of optimum operating points of transistors, revealing circuits with a minimum degradation with respect to aging. A PMOS common source amplifier is designed by setting operating points of all relevant transistors according to the minimal sensitivity with respect to aging. The results show that for given target specification this method provides a well functional measure to reduce the degradation of circuit characteristics.

Analog behavioral modeling for age-dependent degradation of complex analog circuits

Analog circuit performance are degrading by effects like HCI and NBTI. These performance shifts need to be evaluated by the designer to meet given specifications. The evaluation on transistor level enables an accurate prediction of degradation behavior for a chosen circuit. However, this task is very time-consuming for complex analog circuitry. This paper proposes the use of response surface modeling for age-dependent degradation. The generated model is used to extend analog behavioral descriptions and for an accelerated system level analysis. The proposed age-dependent degradation model is demonstrated on a common source amplifier and an analog frontend for the measurement of neural activities. Simulation results demonstrate the accuracy and simulation acceleration of the proposed modeling method.

Reliability analysis for integrated circuit amplifiers used in neural measurement systems

NBTI and HCI are not only present in digital circuits but also in analog circuitry. Integrated circuit amplifiers as used in neural measurement systems (NMS) need to be resistive against degradation since these systems cannot be replaced easily. A topology driven design methodology to increase the reliability of amplifiers used for intracortical neural recording has been proposed in this work. This approach leads to a decrease in degradation for some system performances by a factor of three. It has been shown that the degradation of a circuit is highly dependent on the selected current mirror and biasing circuit.

Two-variable numeric function approximation using least-squares-based regression

Automated design of two-variable numeric functions can be realized efficiently by extending well-known multiplier-less linear function approximation techniques; the arithmetic signal processing effort is minimized by the utilization of a non-uniform piecewise segmentation scheme. However, as common state-of-the-art approaches only consider unpretentious coefficient estimation techniques, such as gradient superposition, this results in large multiplexer-trees for segmentation that, consequently, are restricting the total performance. In this paper a least-squares-based estimation of multiplier-less linear coefficients is introduced that minimizes the number of segments by using a least-squares-based coefficient estimation. The evaluation indicates a reduction of the segmentation effort by nearly 31% on average. Logical and physical CMOS synthesis is performed and the results are compared to actual references highlighting our work high performance approach for the hardware-based calculation of two-variable numeric functions.

Charge-based stochastic aging analysis of CMOS circuits

Scaled down CMOS transistors are prone to degradation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTI and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the gm/Id work flow or for yield estimation on circuit level.