Joe Fulton

Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance

This paper presents a double-RESURF lateral double-diffused MOS (LDMOS) transistor with a specific on-resistance of lower than 200 m/spl Omega/-cm/sup 2/ while maintaining a breakdown voltage of over 750 V for use in the cost-effective high voltage integrated circuit (HVIC) chip. The proposed double-RESURF high voltage device is monolithically integrated with low voltage analog/logic control circuitry, and is 100% backwards-compatible to ON Semiconductors existing single-RESURF technology. Double-RESURF is a very complicated process to implement, and requires a well-designed device layout with complete charge balance among all the critical layers. This paper will demonstrate a painstaking optimization of key process and device geometrical parameters to maximize the benefits of the double-RESURF phenomenon in order to achieve the lowest on-resistance possible with the desired breakdown voltage.