Mohammed Tanvir Quddus

Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process

A simple method for determining the optimal charge balance and processing window of double-reduced surface field (RESURF) lateral devices is presented. The technique is based on the use of simple two test structures that are widely used in ICs, no special test structures are required. The optimal processing window is determined from the bounds over which RESURF is maintainable, and hence, high breakdown voltage is achievable. Using the technique, device designers can set and choose the process conditions of the devices critical layers to yield a manufacturable process prior to actual device layout, and therefore preserves the ability for layout design optimization independent of process optimization. The proposed technique also maximizes the benefits of double-RESURF processing for achieving the lowest on-resistance while maintaining the desired breakdown voltage. Using the technique, the process design and optimization guidelines for a double-RESURF LDMOS built in a high voltage IC technology are discussed and supported with experimental results.

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the devices critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.

Carrier separation technique to optimize conductivity modulation in high voltage rectifiers

Hybrid power rectifier structures like Junction Barrier Schottky (JBS) rectifier and Trench JFET Schottky rectifier (TJFET) employ a combination of minority and majority carrier conduction to offer the superior on-state and switching performance of Schottky rectifiers, along-with the superior reverse leakage and breakdown characteristics of PiN rectifiers. In such structures, it is important to properly tune the conductivity modulation to achieve the desired forward voltage drop (VF) and stored charge (QRR) trade-off for any given application. Some structures also employ lifetime control techniques to improve the switching speeds. This paper presents a new method based on carrier separation technique to properly quantify and optimize the amount of conductivity modulation in hybrid rectifier structures, and can be easily extended to other similar power device structures.

Trench schottky rectifiers with non-uniform trench depths

A design methodology to optimize the drift region doping properties in trench Schottky rectifiers has been presented. Advanced lithography is being used for trench devices that are designed for smaller die sizes in wireless applications. Such devices feature narrow active trenches to maximize active area utilization in combination with a wide termination trench to support the breakdown voltage. Such different trench aspect ratios create a depth mismatch, if they are formed in a single etch step. It has been shown that designing the drift region while accounting for the trench depth difference is vital to properly optimize the device electrical parameters. A new trench architecture has also been proposed which features alternating deeper active trenches. The new trench architecture is shown to have the best performance trade-off at the cost of one additional mask step.

Manufacturing optimization for Silicon Trench rectifiers using NiPt salicide

The purpose of this study was to provide a low cost manufacturing solution for Silicon Trench based Schottky rectifiers utilizing NiPt alloy composition that produces multiple barrier heights and provide designers the option to easily adjust the barrier height (BH) for rectifier designs. Higher temperatures needed to obtain larger barrier heights are generally unfavorable for trench-based Schottky rectifiers. The silicides in trench rectifiers are separated by relativity small distances with nonreactive material (such as silicon oxide) and with high energy anneals and the silicon from the substrate will migrate creating a Ni(Pt)Si bridge between adjacent silicides. Additional issues arise from thicker Ni(Pt)Si growth near the gate oxide interface causing localized high silicon stress. Both these issues cause device performance issues such as increased diode leakage. Most common industry solution is to change the %Pt in the Ni alloy thus modulating the BH. A low cost solution is to use one NiPt alloy to meet multiple BH needs by changing the anneal conditions and adding a Ti “Cap” to the NiPt film.

A novel trench Schottky rectifier structure with controlled conductivity modulation

A Trench MOS Barrier Schottky rectifier (TMBS) structure with a novel conductivity modulation scheme has been presented. The conductivity modulation in the structure is achieved by using remote conductivity modulation (RCM) centers in the mesa regions, with varying frequency and doping profiles to achieve the desired trade-off between forward voltage drop and switching speed of the device. Using the new modulation scheme, devices with low forward voltage drop or low switching speeds can be obtained without the need for any lifetime control in the drift region. The RCM scheme has been implemented in a 200 V, 30 A trench Schottky device, and it has been demonstrated experimentally that by employing the RCM scheme, best-in-class forward voltage drop, breakdown voltage and switching speed are achieved.