Mohamed Imam

Design and optimization of double-RESURF high-voltage lateral devices for a manufacturable process

A simple method for determining the optimal charge balance and processing window of double-reduced surface field (RESURF) lateral devices is presented. The technique is based on the use of simple two test structures that are widely used in ICs, no special test structures are required. The optimal processing window is determined from the bounds over which RESURF is maintainable, and hence, high breakdown voltage is achievable. Using the technique, device designers can set and choose the process conditions of the devices critical layers to yield a manufacturable process prior to actual device layout, and therefore preserves the ability for layout design optimization independent of process optimization. The proposed technique also maximizes the benefits of double-RESURF processing for achieving the lowest on-resistance while maintaining the desired breakdown voltage. Using the technique, the process design and optimization guidelines for a double-RESURF LDMOS built in a high voltage IC technology are discussed and supported with experimental results.

Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices

A simple one-dimensional (1-D) analytical solution method for analyzing and determining the breakdown properties of reduced surface field (RESURF) lateral devices is presented. The solution demonstrates quantitatively and qualitatively the reshaping and reduction of the electric field and its dependence on the device/process key parameters. The solution is based on a simple and physical charge-sharing approach that takes into account the modulation of the lateral depletion layer spreading caused by the vertical depletion extension, and therefore transforms the inherent two-dimensional effects into a simple 1-D equivalent. It also provides a reasonable insight on the breakdown voltage sensitivity of lateral RESURF devices to key device/process parameters that other researchers failed to provide. Using the technique, device designers can set and choose the optimal processing window of the devices critical layers to yield high breakdown voltages. The results obtained using the proposed solution method agree well with the experimental and simulation results.

Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance

This paper presents a double-RESURF lateral double-diffused MOS (LDMOS) transistor with a specific on-resistance of lower than 200 m/spl Omega/-cm/sup 2/ while maintaining a breakdown voltage of over 750 V for use in the cost-effective high voltage integrated circuit (HVIC) chip. The proposed double-RESURF high voltage device is monolithically integrated with low voltage analog/logic control circuitry, and is 100% backwards-compatible to ON Semiconductors existing single-RESURF technology. Double-RESURF is a very complicated process to implement, and requires a well-designed device layout with complete charge balance among all the critical layers. This paper will demonstrate a painstaking optimization of key process and device geometrical parameters to maximize the benefits of the double-RESURF phenomenon in order to achieve the lowest on-resistance possible with the desired breakdown voltage.

Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET's

Experimental and analytical results of the front gate bias (V/sub GS/) and the drain current (I/sub DS/) with the drain voltage (V/sub DS/) of partially depleted (PD) SOI MOSFET at the Zero-Temperature-Coefficient (ZTC) point over a very wide temperature range (25-300/spl deg/C) are presented. Two distinct ZTC points are identified, one in the linear region and the other is in the saturation region. Additionally, the analysis takes into consideration the body effects, and mobility degradation with applied front gate bias. The analysis results are in excellent agreement with the experimental results. >

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

Abstract A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poissons equation and the short-channel solution to the Laplace equation, and the solution of the Poissons equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.

An extended Tanh law MOSFET model for high temperature circuit simulation

The Tanh law MOSFET model proposed earlier by Shousha & Aboulwafa (see ibid., vol. 28, no. 2, p. 176-9, 1993) is extended to predict the temperature dependence of the drain current by including the temperature dependence of the threshold voltage and the mobility. The model requires fewer temperature dependent parameters compared to SPICE level2 model. The extended model shows good agreement between measurement and simulation of devices with different device geometries over wide temperature range (27-200/spl deg/C). >

A simple method to determine the floating-body voltage of SOI CMOS devices

A technique to extract the off-state floating-body (FB) voltage of silicon-on-insulator (SOI) CMOS devices is presented. The bias dependent S-parameter measurements of a single standard FB SOI device and its equivalent circuit, along with the capacitance-voltage (C-V) measurements between the drain and source of the same device, are used to determine the FB voltage. No special test structure design is needed. The technique proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depicted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage.

Determination and assessment of the floating-body voltage of SOI CMOS devices

A self-consistent method to extract the off-state floating-body (FB) voltage of SOI CMOS devices is presented. The technique is simple and is based on CV and S-parameter measurements of a single standard SOI MOSFET device; no special test structure design is needed. The bias dependent S-parameter measurements of the FB SOI device and its equivalent circuit, along with the CV measurements between the drain and source of the same device, are used to determine the FB voltage. The technique provides reasonable insight on device off-state and leakage performances that are important for digital applications. Additionally, it proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depleted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage, demonstrating the importance of understanding FB effects on device off-state and junction leakage performances.

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

Abstract A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted ( near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain ( V ds ) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.

MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model

A modified Berkeley short-channel IGFET model (BSIM1) has been developed to accurately model the I-V characteristics and circuit performance of deep submicron MOSFET devices. The improved model provides a simple and more efficient parameter acquisition procedure for MOSFET global modeling in comparison to the original BSIM1 model. The procedure for extracting the global geometry scalable model parameters is described. The extraction procedure provides a decoupling between DC and AC modeling resulting in more accurate time-domain circuit simulations. The proposed modeling procedure eliminates the negative conductance problem experienced in the original BSIM1. The validity of the model is supported by comparisons between measured and simulated results. The focus of this paper is on the digital applications of the BSIM1 SPICE model.