Joerg Siegert

Bimetallic nanoparticles for optimizing CMOS integrated SnO 2 gas sensor devices

We present gas sensor devices based on ultrathin SnO2 films, which are integrated on CMOS fabricated micro-hotplate (μhp) chips. Bimetallic nanoparticles (NPs) such as PdAu, PtAu, and PdPt have been synthesized for optimizing the sensing performance of these sensors. We demonstrate that functionalization of nanocrystalline SnO2 gas sensing films with PdAu-NPs leads to a strongly improved sensitivity to the toxic gas carbon monoxide (CO) while the cross sensitivity to humidity is almost completely suppressed. We conclude that specific functionalization of CMOS integrated SnO2 thin film gas sensors with different types of NPs is a powerful strategy towards sensor arrays capable for distinguishing several target gases. Such CMOS integrated arrays are highly promising candidates for realizing smart multi-parameter sensing devices for the consumer market.

Manufacturing of 3D integrated sensors and circuits

3D integration of functions such as sensors and circuit elements enables miniaturized and cost-effective smart systems. Wirebonds are replaced by Through Silicon Vias (TSVs) and Wafer Level Packaging (WLP) for shorter conductive paths and reduced form factor. This paper reviews prior art and presents a comprehensive set of data from volume manufacturing of 3D integrated optical sensors and circuits using a “via last” manufacturing flow. 3D specific yield detracting processes such as patterning of open TSVs, wafer bonding, and etching are analyzed and discussed. Functional test yields equivalent to standard CMOS process yields can be achieved.

Fracture mechanics life-time modeling of low temperature Si fusion bonded interfaces used for 3D MEMS device integration

In addition to through silicon vias (TSV), wafer bonding became one of the key process steps within 3D integration technologies that allows stacking image or MEMS sensor chips on top of ASIC. Depending on the package, the wafer bonded interface can be loaded by built-in residual stresses and the risk of defect generation and propagation - caused by stress corrosion of the highly loaded siloxane - can lead to bond delamination and failure of the TSV interconnects. In this paper, the basic processes affecting the long-term strength properties in Si bonded interfaces are discussed and summarized on a specific demonstrator. Using finite-element simulation, it is shown that if low temperature Si fusion bonded components are mechanically stressed for extended times a subcritical crack growth of pre-existing micro-defects can occur. Fracture mechanics approaches were applied to predict the time-dependent strength reduction of initial defects, analyzed by Scanning-Acoustic-Microscopy. In addition, the paper presents a general framework of how the life-time properties of loaded low temperature fusion bonded interfaces can be simulated and how the needed material parameters can be determined. Using this method it is possible to consider the life-time properties already during the design stage, thus, reducing the risk of reliability issues during field use.

Metallization defect detection in 3D integrated components using scanning acoustic microscopy and acoustic simulations

Abstract In the context of More than Moore 3D integration concepts, the μm to nm sized failure detection and analysis represents a highly demanding task. In this work, micron sized artificially induced metallization defects in open TSVs are detected by scanning acoustic microscopy (SAM). Micro X-ray computed tomography (μXCT) and scanning electron microscopy (SEM) are used to validate the SAM results. Notably, the SAM results show that the failures for certain TSVs are located at a different position as illustrated by μXCT and SEM. In order to interpret these controversial results, 2D elastodynamic finite integration technique (EFIT) simulations are performed. We discuss the results by taking the excitation of surface acoustic waves (SAWs) or Rayleigh waves into account which are leading to characteristic interference patterns within the TSV. The simulation and understanding of such interference effects can be highly beneficial for the use of SAM with respect to modern failure detection and analyses.

Gathering effect on dark current for CMOS fully integrated-, PIN-photodiodes

PIN photodiodes are semiconductor devices widely used in a huge range of applications, such as photoconductors, charge-coupled devices, and pulse oximeters. The possibility to combine and to integrate the fabrication of the sensor with its signal conditioning circuitry in a CMOS process flow opens the window to device miniaturization enhancing its properties and lowering the production and assembly costs. This paper presents the design and characterization of silicon based PIN photodiodes integrated in a CMOS commercial process. A high-resistivity, low impurity float zone substrate is chosen as the start material for the PIN photodiode array fabrication in order to fabricate devices with a minimum dark current. The photodiodes in the array are isolated by a guard ring consisting of a n+-p+ diffusions. However, the introduction of the guard ring design, necessary for photodiode-to-photodiode isolation, leads to an increase of the photodiodes dark current. In this article, the new parasitic term on the dark current is identified, formulated, modelled and experimental proven and has finally been used for an accurate design of the guard ring.