Cathal Cassidy

Through Silicon Via Reliability

Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.

3D Sensor application with open through silicon via technology

Today 3D interconnection approaches are considered to provide one of the most promising enabling technologies for “More than Moore” solutions. In particular, 3D integration can provide significant progress in semiconductor device development regarding increased system functionality and integration density. In this paper, we describe an innovative concept for sensor integration based on a quality-proven “open” TSV technology on the basis of a 0.35μm CMOS process. An application-optimized sensor-layer is processed on a specific wafer substrate, whereas the CMOS circuits of the system can remain cost-efficiently on an appropriate 0.35μm CMOS or HV-CMOS technology. Another advantage of the proposed TSV solution is the geometric aspect. As the CMOS is attached to the sensor backside, almost 100% of the chip area can be used for the sensing functionality. In the presented technological approach, the sensor wafer is finalized with processing a top metal layer and successive bond oxide layers. The bond oxide layers are planarized by chemo mechanical polishing (CMP). The CMOS wafer is fabricated using a regular 0.35μm CMOS technology up to the vias before the last metal layer. A nitride layer is deposited in order to protect the integrated circuits from damages during the back grinding process. Prior to bonding, the CMOS wafer is thinned down to a thickness of 250μm and then bonded to the sensor wafer by plasma activated bonding followed by an annealing step to reinforce the bond strength. TSV etching is sequentially performed in three steps: firstly, the oxide of inter-metal dielectrics is opened. Secondly, the bulk silicon of the CMOS wafer is etched using a deep reactive ion etch (DRIE) process selectively stopping on the bond oxide of the sensor wafer. After several cleaning steps the spacer oxide is deposited followed by the spacer and bond oxide etching. For TSV metallisation, Tungsten as deposited in a CVD process is chosen providing uniform conformal coating inside the open TSVs. A sputtered Al forms the top metal and a subsequently produced passivation layer completes the fabrication process. With respect to the photo-lithography process for patterning the top metal and passivation layers, a specifically developed resist spray coating technique is used. This allows protecting the TSVs from damage due to the etching gases. The higher complexity of the lithography is compensated by a more simple and reliable processing regarding the TSV quality. The presented technological flow results in advantageous electrical properties of the TSV interconnects, e.g. low resistivity and a high breakdown voltage combined with excellent inherent reliability. The fabricated sensor devices were characterized by a variety of analytical techniques that have specifically been adapted to the requirements of 3D integrated wafer-bonded systems with TSVs. This approach allowed isolating, localizing and characterizing process related inhomogeneities and potential defects inside the open TSVs and in the wafer bond interface with improved analysis throughput. Electrical shorts of the TSV sidewall metallization to the Si substrate could be identified by Lock-in Thermography (LIT). The exact defect position at the sidewall could be estimated by applying a new defocusing technique to additionally determine the defect depth inside the TSV. As a consequence, the identified sidewall defects could subsequently be analyzed by high resolution transmission electron microscopy (HR TEM) to reveal their root causes. Scanning Acoustic Microscopy (SAM) with improved signal analysis and data evaluation was applied to identify and characterize local delamination defects in the wafer-bonded interface of the 3D sensor. The achieved progress regarding failure analysis methodology supported the technological developments and will contribute to secure quality and yield of 3D integrated devices during future manufacturing.

Through Silicon Via (TSV) defect investigations using lateral emission microscopy

Abstract Infra-red photoemission microscopy has been applied for the localization of defects in 3D integrated circuits containing Through Silicon Vias (TSVs). For these investigations, the familiar (planar) emission microscopy configuration was extended to allow imaging and emission microscopy on vertical TSV sidewalls, from versatile 3D viewpoints. Flexible viewing orientation was achieved by introducing an additional reflecting surface into the optical path. Precise alignment of the angle of incidence at the air–silicon interface, with sufficient accuracy to ensure no problematic refraction-related errors, was possible using this experimental set-up. Three examples are presented, showing defect localizations and underlying physical leakage mechanisms in TSV structures.

Depth-resolved photoemission microscopy for localization of leakage currents in through Silicon Vias (TSVs)

Depth-resolved IR photoemission microscopy was applied for localization of defects causing leakage currents within Through Si Vias (TSVs). Specifically, analyses of the changes in intensity and spatial distribution of the detected emission, as a function of the focal plane position, allow quantification of the depth of defects within the TSV. Physical failure analysis verified the presence of the defects at the coordinates specified by emission microscopy, and allowed defect failure mechanisms to be identified.

Topography and Deformation Measurement and FE Modeling applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)

Topography and Deformation Measurement and FE Modeling were applied for characterization of the warpage vs. temperature behavior of several different die stacks, with or without Through Silicon Vias, for sample temperatures from 25°C…250°C. The warpage behavior is of fundamental importance for the lifetime and reliability expectation of the stack.