Johannes Peter Seif

Efficient Monolithic Perovskite/Silicon Tandem Solar Cell with Cell Area >1 cm2

Monolithic perovskite/crystalline silicon tandem solar cells hold great promise for further performance improvement of well-established silicon photovoltaics; however, monolithic tandem integration is challenging, evidenced by the modest performances and small-area devices reported so far. Here we present first a low-temperature process for semitransparent perovskite solar cells, yielding efficiencies of up to 14.5%. Then, we implement this process to fabricate monolithic perovskite/silicon heterojunction tandem solar cells yielding efficiencies of up to 21.2 and 19.2% for cell areas of 0.17 and 1.22 cm(2), respectively. Both efficiencies are well above those of the involved subcells. These single-junction perovskite and tandem solar cells are hysteresis-free and demonstrate steady performance under maximum power point tracking for several minutes. Finally, we present the effects of varying the intermediate recombination layer and hole transport layer thicknesses on tandem cell photocurrent generation, experimentally and by transfer matrix simulations.

Improved amorphous/crystalline silicon interface passivation by hydrogen plasma treatment

Silicon heterojunction solar cells have high open-circuit voltages thanks to excellent passivation of the wafer surfaces by thin intrinsic amorphous silicon (a-Si:H) layers deposited by plasma-enhanced chemical vapor deposition. We show a dramatic improvement in passivation when H2 plasma treatments are used during film deposition. Although the bulk of the a-Si:H layers is slightly more disordered after H2 treatment, the hydrogenation of the wafer/film interface is nevertheless improved with as-deposited layers. Employing H2 treatments, 4 cm2 heterojunction solar cells were produced with industry-compatible processes, yielding open-circuit voltages up to 725 mV and aperture area efficiencies up to 21%.

Amorphous silicon oxide window layers for high-efficiency silicon heterojunction solar cells

In amorphous/crystalline silicon heterojunction solar cells, optical losses can be mitigated by replacing the amorphous silicon films by wider bandgap amorphous silicon oxide layers. In this article, we use stacks of intrinsic amorphous silicon and amorphous silicon oxide as front intrinsic buffer layers and show that this increases the short-circuit current density by up to 0.43 mA/cm2 due to less reflection and a higher transparency at short wavelengths. Additionally, high open-circuit voltages can be maintained, thanks to good interface passivation. However, we find that the gain in current is more than offset by losses in fill factor. Aided by device simulations, we link these losses to impeded carrier collection fundamentally caused by the increased valence band offset at the amorphous/crystalline interface. Despite this, carrier extraction can be improved by raising the temperature; we find that cells with amorphous silicon oxide window layers show an even lower temperature coefficient than referenc...

Amorphous/crystalline silicon interface defects induced by hydrogen plasma treatments

Excellent amorphous/crystalline silicon interface passivation is of extreme importance for high-efficiency silicon heterojunction solar cells. This can be obtained by inserting hydrogen-plasma treatments during deposition of the amorphous silicon passivation layers. Prolonged hydrogen-plasmas lead to film etching. We report on the defect creation induced by such treatments: A severe drop in interface-passivation quality is observed when films are etched to a thickness of less than 8 nm. Detailed characterization shows that this decay is due to persistent defects created at the crystalline silicon surface. Pristine interfaces are preserved when the post-etching film thickness exceeds 8 nm, yielding high quality interface passivation.

Amorphous/Crystalline Silicon Interface Passivation: Ambient-Temperature Dependence and Implications for Solar Cell Performance

Silicon heterojunction (SHJ) solar cells feature amorphous silicon passivation films, which enable very high voltages. We report how such passivation increases with operating temperature for amorphous silicon stacks involving doped layers and decreases for intrinsic-layer-only passivation. We discuss the implications of this phenomenon on the solar cells temperature coefficient, which represents an important figure-of-merit for the energy yield of devices deployed in the field. We show evidence that both open-circuit voltage (Voc) and fill factor (FF) are affected by these variations in passivation and quantify these temperature-mediated effects, compared with those expected from standard diode equations. We confirm that devices with high Voc values at 25°C show better high-temperature performance. However, we also argue that the precise device architecture, such as the presence of charge-transport barriers, may affect the temperature-dependent device performance as well.

Nanocrystalline Silicon Carrier Collectors for Silicon Heterojunction Solar Cells and Impact on Low-Temperature Device Characteristics

Silicon heterojunction solar cells typically use stacks of hydrogenated intrinsic/doped amorphous silicon layers as carrier selective contacts. However, the use of these layers may cause parasitic optical absorption losses and moderate fill factor (FF) values due to a high contact resistivity. In this study, we show that the replacement of doped amorphous silicon with nanocrystalline silicon is beneficial for device performance. Optically, we observe an improved short-circuit current density when these layers are applied to the front side of the device. Electrically, we observe a lower contact resistivity, as well as higher FF. Importantly, our cell parameter analysis, performed in a temperature range from -100 to +80 °C, reveals that the use of hole-collecting p-type nanocrystalline layer suppresses the carrier transport barrier, maintaining FF s in the range of 70% at -100 °C, whereas it drops to 40% for standard amorphous doped layers. The same analysis also reveals a saturation onset of the open-circuit voltage at -100 °C using doped nanocrystalline layers, compared with saturation onset at -60 °C for doped amorphous layers. These findings hint at a reduced importance of the parasitic Schottky barrier at the interface between the transparent electrodes and the selective contact in the case of nanocrystalline layer implementation.

Transparent Electrodes in Silicon Heterojunction Solar Cells: Influence on Contact Passivation

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solar cells. Based on our findings, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.

Low-temperature plasma-deposited silicon epitaxial films: Growth and properties

Low-temperature (≤200 °C) epitaxial growth yields precise thickness, doping, and thermal-budget control, which enables advanced-design semiconductor devices. In this paper, we use plasma-enhanced chemical vapor deposition to grow homo-epitaxial layers and study the different growth modes on crystalline silicon substrates. In particular, we determine the conditions leading to epitaxial growth in light of a model that depends only on the silane concentration in the plasma and the mean free path length of surface adatoms. For such growth, we show that the presence of a persistent defective interface layer between the crystalline silicon substrate and the epitaxial layer stems not only from the growth conditions but also from unintentional contamination of the reactor. Based on our findings, we determine the plasma conditions to grow high-quality bulk epitaxial films and propose a two-step growth process to obtain device-grade material.

The impact of silicon solar cell architecture and cell interconnection on energy yield in hot & sunny climates

Extensive knowledge of the dependence of solar cell and module performance on temperature and irradiance is essential for their optimal application in the field. Here we study such dependencies in the most common high-efficiency silicon solar cell architectures, including so-called Aluminum back-surface-field (BSF), passivated emitter and rear cell (PERC), passivated emitter rear totally diffused (PERT), and silicon heterojunction (SHJ) solar cells. We compare measured temperature coefficients (TC) of the different electrical parameters with values collected from commercial module data sheets. While similar TC values of the open-circuit voltage and the short circuit current density are obtained for cells and modules of a given technology, we systematically find that the TC under maximum power-point (MPP) conditions is lower in the modules. We attribute this discrepancy to additional series resistance in the modules from solar cell interconnections. This detrimental effect can be reduced by using a cell design that exhibits a high characteristic load resistance (defined by its voltage-over-current ratio at MPP), such as the SHJ architecture. We calculate the energy yield for moderate and hot climate conditions for each cell architecture, taking into account ohmic cell-to-module losses caused by cell interconnections. Our calculations allow us to conclude that maximizing energy production in hot and sunny environments requires not only a high open-circuit voltage, but also a minimal series-to-load-resistance ratio.

Asymmetric band offsets in silicon heterojunction solar cells: Impact on device performance

Amorphous/crystalline silicon interfaces feature considerably larger valence than conduction band offsets. In this article, we analyze the impact of such band offset asymmetry on the performance of silicon heterojunction solar cells. To this end, we use silicon suboxides as passivation layers—inserted between substrate and (front or rear) contacts—since such layers enable intentionally exacerbated band-offset asymmetry. Investigating all topologically possible passivation layer permutations and focussing on light and dark current-voltage characteristics, we confirm that to avoid fill factor losses, wider-bandgap silicon oxide films (of at least several nanometer thin) should be avoided in hole-collecting contacts. As a consequence, device implementation of such films as window layers—without degraded carrier collection—demands electron collection at the front and hole collection at the rear. Furthermore, at elevated operating temperatures, once possible carrier transport barriers are overcome by thermioni...