John A. Allgair

Determination of optimal parameters for CD-SEM measurement of line-edge roughness

The measurement of line-edge roughness (LER) has recently become a topic of concern in the litho-metrology community and the semiconductor industry as a whole. The Advanced Metrology Advisory Group (AMAG), a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST), has a project to investigate LER metrics and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed, standardized solution for implementation. The 2003 International Technology Roadmap for Semiconductors (ITRS) has included a new definition for roughness. The ITRS envisions root mean square measurements of edge and width roughness. There are other possible metrics, some of which are surveyed here. The ITRS envisions the root mean square measurements restricted to roughness wavelengths falling within a specified process-relevant range and with measurement repeatability better than a specified tolerance. This study addresses the measurement choices required to meet those specifications. An expression for the length of line that must be measured and the spacing of measurement positions along that length is derived. Noise in the image is shown to produce roughness measurement errors that have both random and nonrandom (i.e., bias) components. Measurements are reported on both UV resist and polycrystalline silicon in special test patterns with roughness typical for those materials. These measurements indicate that the sensitivity of a roughness measurement to noise depends importantly both on the choice of edge detection algorithm and the quality of the focus. Measurements are less sensitive to noise when a model-based or sigmoidal fit algorithm is used and when the images are in good focus. Using the measured roughness characteristics for UV resist lines and applying the ITRS requirements for the 90 nm technology node, the derived expression for sampling length and sampling interval implies that a length at least 8 times the node (i.e., 720 nm) must be measured at intervals of 7.5 nm or less.

Implementation of spectroscopic critical dimension (SCD) (TM) for gate CD control and stepper characterization

Smaller device dimensions and tighter process control windows have created a need for CD metrology tools having higher levels of precision and accuracy. Furthermore, the need to detect and measure changes in feature profiles is becoming critical to in-line process control and stepper evaluation for sub-0.18micrometers technology. Spectroscopic CD (SCDTM) is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure and characterize the focus and exposure windows for the process. The results include comparison to the established in-line CD-SEM, as well as a cross-section SEM. Repeatability and long-term stability data form a gate level nominal process are also presented.

Manufacturing considerations for implementation of scatterometry for process monitoring

The continuing demand for higher frequency microprocessors and larger memory arrays has led to decreasing device dimensions and smaller process control windows. Decreasing process control windows have created a need for higher precision metrology to maintain an acceptable precision to tolerance ratio with a reasonable sampling rate. In order to determine and reduce across chip, across wafer, and across lot linewidth variations, higher sampling is required which, in turn, demands faster move acquire measure (MAM) times to maintain throughput. Finally, the need to detect and quantify sidewall angle changes in addition to CD measurements is becoming critical. Spectroscopic Scatterometry is a metrology technique which offers the potential to meet these requirements. This work explores some of the fundamental technology concerns for implementing scatterometry in a manufacturing environment. These concerns include mark requirements and characterization necessary for library generation. Comparison of scatterometry data to in-line CD SEM, x-section SEM, and AFM results will be presented.

Performance study of new segmented overlay marks for advanced wafer processing

We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.

Characterization of optical proximity correction features

One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process window for acceptable imaging of the full 2D structure is more limited than the process window for CDs alone. The shape and area of the feature have become as critical to the proper patterning as the width. The measurement and analysis of Critical Shape Difference (CSD) of patterned features must be an integral part of process development efforts. Adoption of optical proximity correction (OPC) and other Optical Extension Technologies increases the need for understanding specific effects through the pattern transfer process. Sub-resolution features on the mask are intended to compensate the pattern so that the resulting etched features most accurately reflect the designers intent and provide the optimum device performance. A method for quantifying the Critical Shape Difference between the designers intent, OPC application, mask preparation, resist exposure and pattern etch has been developed. This work focuses on overlaying features from the various process stages and using CSD to quantify the regions of overlap in order to assess OPC performance. Specific examples will demonstrate the gap in current 1-D analysis techniques.

Feature integrity monitoring for process control using a CD SEM

Rapidly accelerating technology roadmaps have put increased pressure on in-line process control. CDs measured by automated SEMs are a common element of in-line process control. However, CD measurements alone may not be enough in all cases for adequate process control. For instance, degradation of feature integrity that does not lead to out of control CDs in photo can lead to scrap after etch. The cost of scrap and loss of time to results associated with catching photo process drift with after etch inspection has forced the development of new tools to monitor feature integrity in the ADI CD inspection module. Likewise, partially closed vias that are not caught with etch CD inspection can have a negative impact on copper processes. We describe a feature integrity monitoring technique using an automated CD-SEM that occurs simultaneously with the CD measurement to monitor and detect process drift prior to out of control CD events. We further describe the implementation of this technique in a production environment.

Results of benchmarking of advanced CD-SEMs at the 90-nm CMOS technology node

The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH Manufacturing Initiative (ISMI) consortium’s Member Companies and from the National Institute of Standards (NIST). The AMAG wrote and, in 2002, with CD-SEM supplier involvement, updated the “Unified Advanced CD-SEM Specification for Sub-130nm Technology (Version 2002)” to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2003 International Technology Roadmap for Semiconductors, and also conveys member companies’ other collective needs to vendors. Through applying this specification during the mid-2003 timeframe, a benchmarking effort of the currently available advanced CD-SEMs has been performed. These results are presented here. The AMAG Unified Specification includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter included in the benchmark, and, when applicable, prescribes a target specification compatible with the ITRS and methodologies compatible with the demands of 90nm technology. Parameters to be considered include: •Precision, Repeatability and Reproducibility •Accuracy, Apparent Beam Width and Resolution •Charging and Contamination •Tool-to-Tool Matching •Pattern Recognition and Navigation Accuracy •Throughput •Instrumentation Outputs •Tool Automation and Utility •Precision and Accuracy of Profile Measurement •Precision and Accuracy of Roughness Measurement. Previous studies under this same project have been published, with the initial version of the International Sematech Unified Specification in 1998, and multi-supplier benchmarks in 1999 and 2001. The results for the 2003 benchmark will be shown and compared to the ITRS, and composite viewpoints showing these 2003 benchmark results compared to the past results are also shown, demonstrating interesting CD-SEM industry trends.

Toward a unified advanced CD-SEM specification for sub-0.18-μm technology

The stringent critical dimension control requirements in cutting edge device facilities have placed significant demands on metrologists and upon the tools they use. We are developing a unified, advanced critical dimension scanning electron microscope specification in the interests of providing a unified criterion of performance and testing. The specification is grounded on standard definitions and strong principles of metrology. The current revision is to be published as a SEMATECH document. A new revision, now in progress, will embody the consensus of a vendor/user conference.

Characterization of CD control for sub-0.18 μm lithographic patterning

It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.

Characterization of overlay tolerance requirements for via to metal alignment

Decreasing metal interconnect dimensions have led to tighter overlay tolerance requirements to ensure via to metal contact. These strict requirements often test the alignment capability of a manufacturing line; therefore, careful characterization is required to justify the overlay specification limits. A variety of technique can be combined for overlay process characterization including electrical resistance measurements, optical overlay measurements, CD SEM via misalignments and x-section yield. Available characterization techniques are then used to fully study the process window. Characterization data will be presented for a copper interconnect process.