Robert R. Hershey
Motorola
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Featured researches published by Robert R. Hershey.
Metrology, inspection, and process control for microlothoggraphy. Conference | 2001
John A. Allgair; David C. Benoit; Mark Drew; Robert R. Hershey; Lloyd C. Litt; Pedro Herrera; Umar K. Whitney; Marco Guevremont; Ady Levy; Suresh Lakkapragada
Smaller device dimensions and tighter process control windows have created a need for CD metrology tools having higher levels of precision and accuracy. Furthermore, the need to detect and measure changes in feature profiles is becoming critical to in-line process control and stepper evaluation for sub-0.18micrometers technology. Spectroscopic CD (SCDTM) is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure and characterize the focus and exposure windows for the process. The results include comparison to the established in-line CD-SEM, as well as a cross-section SEM. Repeatability and long-term stability data form a gate level nominal process are also presented.
Metrology, inspection, and process control for microlithography. Conference | 2000
John A. Allgair; David C. Benoit; Robert R. Hershey; Lloyd C. Litt; Ibrahim Abdulhalim; William Braymer; Michael Faeyrman; John C. Robinson; Umar K. Whitney; Yiping Xu; Piotr Zalicki; Joel L. Seligson
The continuing demand for higher frequency microprocessors and larger memory arrays has led to decreasing device dimensions and smaller process control windows. Decreasing process control windows have created a need for higher precision metrology to maintain an acceptable precision to tolerance ratio with a reasonable sampling rate. In order to determine and reduce across chip, across wafer, and across lot linewidth variations, higher sampling is required which, in turn, demands faster move acquire measure (MAM) times to maintain throughput. Finally, the need to detect and quantify sidewall angle changes in addition to CD measurements is becoming critical. Spectroscopic Scatterometry is a metrology technique which offers the potential to meet these requirements. This work explores some of the fundamental technology concerns for implementing scatterometry in a manufacturing environment. These concerns include mark requirements and characterization necessary for library generation. Comparison of scatterometry data to in-line CD SEM, x-section SEM, and AFM results will be presented.
Metrology, inspection, and process control for microlithography. Conference | 1998
John L. Sturtevant; Michele R. Weilemann; Kent G. Green; John Dwyer; Eric Robertson; Robert R. Hershey
The traditional approach for CD and overlay control in lithography has been based upon statistical control of the critical inputs to the lithographic process. This SPC approach has the disadvantage that the process equipment must be taken out of manufacturing whenever a parameter goes out of control, so that the root cause may be diagnosed and addressed. In the case of leading-edge lithography, it is often not trivial to determine the cause of such disturbances, and productivity can be greatly increased if output data is used to dynamically tune the system inputs. We have successfully implemented a fully automated, closed-loop CD and overlay control system in manufacturing for both I-line and DUV lithography. This system features automatic metrology data upload, host control of stepper/track clusters, and utilizes tool-based lot data for manipulation of future lot inputs. CD control to within 1 nm of target and less than 20 nm 3(sigma) lot to lot variability has been demonstrated. Mean overlay errors of less than 50 nm have been realized as well. Process Cpk values were improved in some cases by more than 50% with implementation of the controller.
Integrated Circuit Metrology, Inspection, and Process Control IX | 1995
Robert R. Hershey; Richard C. Elliott
This paper presents the methodology used to perform an evaluation of automated CD metrology SEMs for sub-half micron process control. The paper describes the evaluation strategy, the procedure used to collect and analyze the evaluation data and concludes with recommendations on how the procedure can be improved. The evaluation process was designed to estimate metrology capability and review specific application requirements envisioned for a leading edge semiconductor development and manufacturing facility at Motorola. The evaluation process consisted of a quantitative evaluation of measurement performance specifically examining the reproducibility, linearity, automation success rate, and throughput of the instrument. In addition, capabilities such as user interface, computer integration, job transportability, and technology roadmap were assessed qualitatively. Although a particular evaluation of automated CD SEMs is considered here, the principles used to develop the evaluation procedure can be applied to metrology tools in general. A discussion of the application and desired functionality of CD metrology instrumentation including performance criteria is presented for completeness.
Proceedings of SPIE, the International Society for Optical Engineering | 1999
John L. Sturtevant; John A. Allgair; Chong-Cheng Fu; Kent G. Green; Robert R. Hershey; Michael E. Kling; Lloyd C. Litt; Kevin D. Lucas; Bernard J. Roman; Gary Stanley Seligman; Mike Schippers
It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.
Optical Microlithography X | 1997
John L. Sturtevant; John A. Allgair; Mark William Barrick; Chong-Cheng Fu; Kent G. Green; Robert R. Hershey; Lloyd C. Litt; John Maltabes; Carla Nelson-Thomas; Bernard J. Roman; John Singelyn
DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.
Microelectronic Engineering | 1998
John Maltabes; T.L. Perkinson; Lloyd C. Litt; Robert R. Hershey; S. Murphy
Abstract Traditional methods of making tool selections for semiconductor manufacturing facilities tend to focus on minimizing equipment capital costs or minimizing wafer costs. A model that comprehends the effects of tool performance, product specifications, processing costs, and die yield to analyze alternate tooling strategies for lithography exposure equipment has been developed. This model enables the investigation of the profit implications of a given tool strategy. The economic framework for this model is reviewed, as are the inputs required for the lithography-specific implementation. Generalized specifications are developed for some generic I-line and DUV tools, and a process flow is defined for a generic logic device. The model is then applied using two types of analysis. The first application quantifies the differences in fab costs for several altermate tool selections. The second application investigates several multi-year tooling strategies.
Integrated Circuit Metrology, Inspection, and Process Control VII | 1993
Robert R. Hershey; Michael B. Weller
This paper discusses nonlinear behavior in SEM CD measurements stemming from the interaction of the edge detection algorithm and systematic changes in the appearance of the secondary electron signal. A first-order theory is developed which describes the effect of changes in apparent sidewall slope and baseline level on common edge detection algorithms. Specifically the theory predicts nonlinear behavior for linear approximation and threshold edge detection algorithms. Experimental verification of the effect is presented. Systematic increases in linewidth of 10% are frequently encountered in practice when making measurements in the sub 0.75 micrometers regime.
Integrated Circuit Metrology, Inspection, and Process Control VIII | 1994
Robert R. Hershey; Richard C. Elliott
This paper describes a new method for monitoring the performance of metrology systems. The objective of the technique is to both identify deviant performance and estimate the likely cause. The method is driven by the assumption that all variation in a measurement system is systematic until proven random. This assumption in turn guides the choice of sampling plan and analysis to extract the maximum amount of information possible from a given number of measurements. Diagnostic capability is achieved by selecting a sampling plan which yields data for estimates of all known error modes of the instrument. Consequently, somewhat larger sampling plans are required and the technique is generally more appropriate for automated measurement systems. The concept is illustrated by example using automated scanning electron microscopes used for critical dimension measurement in the semiconductor manufacturing process. Experimental results illustrating the response of the monitor to programmed deviation are presented.
Integrated Circuit Metrology, Inspection, and Process Control VI | 1992
Robert R. Hershey; Terrence E. Zavecz
The considerations which drive an expert system for assisting in measurement system characterization are described. The expert system employs several novel techniques for evaluating the integrity of a characterization analysis by determining the degree to which critical assumptions are satisfied and flagging weak points in the data collection or analysis procedure. The properties of good characterization sampling plans are derived. Methods for formulating reliable characterization studies are described. The paper focuses on short term studies intended for equipment comparisons and calibrations; however, with minor alterations it can be expanded to include longer term stability studies.