John Crossley

A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19W/mm 2 at 73% efficiency

Lithium-ion batteries are the dominant power source in mobile devices. However, while the supply voltage required for processors and SoCs has scaled down to ~1V, the voltage range of this popular battery remains ~2.9V-4.2V (nominally ~3.6V). To bridge this voltage difference, off-chip power management ICs are typically required. Despite their high efficiency, supporting many independent, high-current supplies to e.g. a multi-core SoC is extremely challenging due to cost, area, and supply impedance concerns associated with board and package level parasitics. There is hence strong motivation for efficient, fully integrated voltage regulators (IVRs) that interface directly with the battery while supporting multiple separate on-chip supply.

A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects

We present an ultra-wideband transceiver designed for ultra-low-power communication at sub-10 cm range. The transceiver operates at a 5.6 GHz carrier frequency, chosen to minimize path loss when using a 1 cm2 antenna, and can switch its architecture between self-synchronous rectification and low-IF to adapt its power consumption to the channel characteristic in real time. A low-power digital circuit exploits redundancy in the modulation scheme to provide a real-time BER estimate used to close the mode-switching loop. Implemented in 65 nm CMOS, the transceiver consumes 25 μW when transmitting and 245 μW when receiving in low-power mode, plus 45 μW in the clock generator, and only requires an external antenna. Dual-mode operation allows range extension and mitigates interference.

An energy-efficient ring-oscillator digital PLL

A linear but fully digital phase control path and a bang-bang frequency control path enable an energy-efficient digital ring-oscillator PLL architecture. A 65nm CMOS prototype occupies 150µm × 170µm of area and generates a 3GHz clock from a 300MHz reference with 1.13ps rms period jitter while consuming 2mW from a single 1V power supply.

BAG: a designer-oriented integrated framework for the development of AMS circuit generators

We introduce BAG, the Berkeley Analog Generator, an integrated framework for the development of generators of Analog and Mixed Signal (AMS) circuits. Such generators are parameterized design procedures that produce sized schematics and correct layouts optimized to meet a set of input specifications. BAG extends previous work by implementing interfaces to integrate all steps of the design flow into a single environment and by providing helper classes - both at the schematic and layout level - to aid the designer in developing truly parameterized and technology-independent circuit generators. This simplifies the codification of common tasks including technology characterization, schematic and testbench translation, simulator interfacing, physical verification and extraction, and parameterized layout creation for common styles of layout. We believe that this approach will foster design reuse, ease technology migration, and shorten time-to-market, while remaining close to the classical design flow to ease adoption. We have used BAG to design generators for several circuits, including a Voltage Controlled Oscillator (VCO) and a Switched-Capacitor (SC) voltage regulator in a CMOS 65nm process. We also present results from automatic migration of our designs to a 40nm process.

A fully integrated, 300pJ/bit, dual mode wireless transceiver for cm-range interconnects

A transceiver aimed at ultra-short range wireless links uses a dual-mode architecture to achieve interference robustness at ultra-low power. The receiver uses a direct-AM detection architecture combined with a high-pass baseband filter to suppress out-of-band interferers, but is reconfigured to use a mixer-high-pass filter cascade designed to suppress in-band blockers based on a real-time BER estimate. The system consumes 300uW at 1MBps (1.75mW at 16 Mbps) and can operate with a worst-case SIR of 13dB (referred to peak power).