John Edward Cronin

Dual Damascene: a ULSI wiring technology

Escalating density, performance, and (perhaps most importantly) manufacturing requirements associated with ULSI semiconducting wiring, necessitate a metamorphosis in interconnection technology. To meet these needs, an inlaid fully integrated wiring technology called Dual Damascene has been designed and demonstrated at IBMs Essex Junction, Vermont, facility. A subset of the technologys features has been successfully implemented in the manufacture of IBMs 4-Mb DRAM. The Dual Damascene structure achieved is a planar, monolithic-metal interconnect, comprising a vertical metal stud and horizontal metal interconnect, both embedded in an insulator matrix. The complete Dual Damascene technology features a unique process sequence, chemical-mechanical insulator planarization, stacked photolithographic masks, clustered stud and interconnect etch, concurrent stud and interconnect metal fill, and chemical-mechanical metal etchback.<<ETX>>

Submicron wiring technology with tungsten and planarization

A submicron wiring technology has been designed, built, and proven reliable. This fully integrated technology features CVD-tungsten (W) and planarization. Vertical W studs maximize density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability.A versatile wiring technology has been developed which is suitable for high-density memory and multilevel logic applications. This fully integrated technology features CVD-tungsten (W) and planarization. Virtual W studs maximise density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability. The chosen materials and process combinations make possible aggressive metal pitch for DRAM, reliable space saving vertical studs for contact/via intensive SRAM, and provide vertical wiring for high-density multilevel logic. Device and reliability results are presented.<<ETX>>

Chemical Vapor Deposition of Tungsten (CVD W) as Submicron Interconnection and Via Stud

Blanket-deposited chemical vapor deposition of tungsten (CVD W) has been developed and implemented in a 4-Mbit DRAM and equivalent submicron VLSI technologies. CVD W was applied as contact stud, interconnect, and interlevel via stud. The technologies have been proven reliable under several reliability stress conditions. Major technical problems involved in CVD W processing, such as adhesion, contact resistance, etchability, and hole fill are discussed. A novel technique that uses TiN as a contact and adhesion layer is presented. This technique has lead to the resolution of the above technical problem and significantly improved the manufacturability of blanket CVD W processes.