William J. Cote

Dual Damascene: a ULSI wiring technology

Escalating density, performance, and (perhaps most importantly) manufacturing requirements associated with ULSI semiconducting wiring, necessitate a metamorphosis in interconnection technology. To meet these needs, an inlaid fully integrated wiring technology called Dual Damascene has been designed and demonstrated at IBMs Essex Junction, Vermont, facility. A subset of the technologys features has been successfully implemented in the manufacture of IBMs 4-Mb DRAM. The Dual Damascene structure achieved is a planar, monolithic-metal interconnect, comprising a vertical metal stud and horizontal metal interconnect, both embedded in an insulator matrix. The complete Dual Damascene technology features a unique process sequence, chemical-mechanical insulator planarization, stacked photolithographic masks, clustered stud and interconnect etch, concurrent stud and interconnect metal fill, and chemical-mechanical metal etchback.<<ETX>>

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Abstract Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimization and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical-mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies.

Submicron wiring technology with tungsten and planarization

A submicron wiring technology has been designed, built, and proven reliable. This fully integrated technology features CVD-tungsten (W) and planarization. Vertical W studs maximize density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability.A versatile wiring technology has been developed which is suitable for high-density memory and multilevel logic applications. This fully integrated technology features CVD-tungsten (W) and planarization. Virtual W studs maximise density by reducing contact/via ground rules and by facilitating the use of thick insulators for minimum capacitance. Complementary insulator and W planarization eliminate steps and ease patterning. As a result, circuit performance is enhanced without sacrificing yield or reliability. The chosen materials and process combinations make possible aggressive metal pitch for DRAM, reliable space saving vertical studs for contact/via intensive SRAM, and provide vertical wiring for high-density multilevel logic. Device and reliability results are presented.<<ETX>>

Low-temperature chemical vapor deposition processes and dielectrics for microelectronic circuit manufacturing at IBM

Significant progress has been made over the past decade in low-temperature plasma-enhanced and thermal chemical vapor deposition (CVD). The progress has occurred in response to the high demands placed on the insulators of multilevel microelectronic circuits because of the continuing reduction in circuit dimensions. High-aspect-ratio gap filling is foremost among these demands, which also include lower processing temperatures and improved dielectric planarization. This paper reviews the history of interlevel and intermetal dielectrics used in microelectronic circuit manufacturing at IBM and the current status of processes used in IBM manufacturing and development lines, and describes the challenges for future memory and logic chip applications.

A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.

A 4 Mb Low-temperature DRAM

The authors present the characterization of the first dynamic RAM (DRAM) fabricated in a technology specifically optimized for cryogenic operation. With the power supply adjusted to assure hot-electron reliability, the 25-ns 4-Mb low-temperature (LT) chips operated 3 times faster than conventional chips. The LT-optimized chips functioned properly with cycle times as fast as 45 ns, and with a toggle-mode data rate of 667 Mb/s. Wide operating margins and a very large process window for data retention were demonstrated. At a temperature of 85 K the storage retention time of the trench-capacitor memory cells exceeded 8 h. This study shows that the performance leverage offered by low temperature applies equally well to DRAM and to logic. There is no limitation inherent to memory. >

Short-flow test chip utilizing fast testing for defect density monitoring in 45nm

A comprehensive 45 nm short-flow test chip was designed and is currently used to improve defect-limited yield. In a novel development to reduce test time, the DC test structures are tested in parallel mode on a functional test platform, resulting in a 5x reduction in test time over conventional parametric testing. The large critical area enables accurate measurement of defect densities down to the ppb-level, while the reduced cycle time of this short-flow test chip makes it an excellent routine defect monitor as well as a test vehicle for evaluating process changes.

A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with >8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.