James Gardner Ryan

The evolution of interconnection technology at IBM

Advances in interconnection technology have played a key role in allowing continued improvements in integrated circuit density, performance, and cost. ibm contributions to interconnection technology over approximately the last ten generations of semiconductor products are reviewed. the development of a planar, back-end-of-line (beol) technology, used in ibm dram, bipolar, and cmos logic products since 1988, has led to a threefold increase in the number of wiring levels, aggressive wiring pitches at all interconnection levels, and high-leverage design options such as stacked contacts and vias. possible future beol technologies are also discussed, with emphasis on the use of higher-conductivity wiring and lower-dielectric-constant insulators. it is expected that their use will result in higher performance and reliability. applications include future, lower-power devices as well as more cost-effective, higher-performance versions of present-day designs.

The preparation and characterization of titanium boride films

Abstract Metal boride films have been shown to be useful in many applications where refractory properties are required. Potential microelectronics applications include use as a diffusion barrier and as a boron diffusion source. In this study, the boron outdiffusion behavior of several compositions of titanium boride films was investigated. TiB 2.1 films did not react with the silicon substrate upon annealing up to 1092°C, but TiB films reacted with silicon at elevated temperatures, apparently to form a titanium silicide. The surface concentration of boron in the silicon substrate increased as the boron-to-titanium ratio in the boride film increased. The boron diffusivities obtained from TiB 2.1 and TiB 2.9 sources are greater than values observed for other types of boron diffusion source when analyzed with the vacancy model. Resistivity studies showed that thicker titanium diboride films had lower resistivities than thinner films when annealed above 1000°C. Post-anneal film stress was independent of anneal temperature above 900°C. The resistivity and film stress values obtained for titanium diboride films were similar to the values observed for refractory metal silicides.

Semiconductor interlevel shorts caused by hillock formation in Al-Cu metallization

A new failure mode in AlCu and AlCuSi metallization is described in which interlevel metal short circuiting occurs between two or more levels of metal. Shorts are caused by theta-phase (Al/sub 2/Cu) hillocks which nucleate and grow during high-temperature vacuum heat treatment and processing, Hillock growth occurs at high-energy sites, such as silicon precipitates and grain boundary nodal points. The growth of Al/sub 2/Cu hillocks depends on the heat-treatment/processing temperature and aluminum film purity. The growth kinetics indicates that grain boundary diffusion is the dominant mass transport mechanism. Methods used to limit theta-phase hillock formation and growth concentrate on the diffusion and nucleation mechanisms involved. Decreasing the heat-treatment/processing temperature slows the atomic diffusion required for hillock growth, and it delays, but does not prevent, theta-phase hillock formation. A 1-h heat treatment (213 Pa, N/sub 2/ ambient) at 350 degrees C produces a high density of large hillocks. Hillock density and height are generally reduced at 300 degrees C. Altering the layered structure of a metallization alters Al/sub 2/Cu hillock growth. Deposition of a hard coating as a cap on the layered structure of an aluminum-based metallization mechanically suppresses hillock formation. A layer of pure aluminum deposited beneath the aluminum-copper layer acts as a sink for copper and delays hillock formation. Increasing film copper content reduces hillock formation: theta-phase hillocks, up to 1.3 mu m in height, are observed in films with 1 wt.% copper, whereas negligible ( >

The effects of alloying on stress induced void formation in aluminum‐based metallizations

Evaporated metallizations composed of aluminum alloys and titanium underlayers were patterned, passivated with plasma enhanced chemical vapor deposited SiNx and aged for 1000 h at 150 °C in order to observe stress‐induced void formation. Metal films were analyzed using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectrometry. The addition of copper to aluminum results in fewer voids than in comparable noncopper metallizations. For Al–Cu films, fewer voids were observed in 1.5 μm lines compared to 5 μm lines, apparently due to the presence of greater stress gradients in the wide line case. Silicon appears to promote void formation by rapid grain boundary diffusion to precipitates. Oxygen incorporation in aluminum produces small grained films, thereby generating many void nucleation sites. High oxygen concentrations produce films with a few long, channel‐like voids and many small voids. Titanium underlayers decrease the percent of metal volume voided for Al and AlS...

Recent advances in the application of collimated sputtering

Abstract The “W-Capped Aluminum Damascene Process” forms low-resistance wiring for the IBM/Siemens 64 MB dynamic random access memory (DRAM). Damascene wiring is fabricated by etching a trough in a dielectric, filling the trough with metal, and planarizing back to the dielectric surface. For the 64 Mb DRAM, collimation is used to enhance fill of the recessed features. This paper reports the results of our recent work to optimize the processes. Specifically, we have investigated the trough-fill capability of the Al and Ti films as a function of process parameters, deposition hardware, and the oxide trough aspect ratios. In addition, we have improved the manufacturability of these processes by modifying the collimator design to increase deposition rate and lengthen collimator life. Finally, we report the first demonstration of an Al-based dual-damascene structure combining collimated sputtering and chemical vapor deposition (CVD) W. Dual damascene combines fabrication of the wires and studs by etching both recesses in the same dielectric and filling them simultaneously, thereby simplifying the process flow and lowering fabrication costs.

The formation and characterization of rare earth boride films

Thin films of several rare earth borides were prepared by either dual-electron-beam evaporation (YB2, YB4 and YB6) or sputtering from a boride target (LaB6). Although values for bulk resistivities and work functions for rare earth borides are low (e.g.ϱ = 17 μΩ cm and o = 2.66 eV for LaB6) thin films of rare earth borides show significantly higher resistivities and work functions (ϱ = 96 μΩ cm and o = 3.8 eV for LaB6 films). Large resistivity increases were observed for rare earth boride films subjected to a 30 min steam oxidation at 1000°C. Adding silicon to the boride films allowed the film to remain conductive even after a 30 min, 1000°C steam oxidation. Also, silicon additions to LaB6 films resulted in a reduction in the film stress after a 1000°C anneal. The stresses within LaB6 and YB2 films were found to be tensile after a 30 min, 1000°C nitrogen anneal (σYB2 = 1.3 x 109 N m-2; σLaB6 = 8 x 108 N m-2). LaB6 films are shown to behave as semi-infinite diffusion sources for boron.

Redistribution phenomena in aluminum alloy/titanium thin films

The chemical and structural changes occurring in aluminum alloy/titanium layered metallizations and their implications are discussed. Characterization of Ti/Al–Cu/Si films was performed by secondary ion mass spectrometry (SIMS), Rutherford backscattering spectrometry, and transmission electron microscopy. Silicon and/or copper additions to aluminum produce a retarded reaction rate between aluminum and titanium upon annealing. SIMS measurements of annealed films show titanium diffusion throughout the entire aluminum film. In the absence of either silicon or copper, the titanium content is homogeneous at a level of ∼6×1018 atoms/cm3. Addition of silicon does not prevent titanium diffusion, but reduces the Ti concentration in the bulk of the film while producing a higher concentration in the near‐surface region. Copper additions produce a similar, but much less dramatic effect.

The Effect of Collimation On Sputtered Alcusi and Almg Microstructures And Electromigration Failure Characteristics

Increasing circuit densities produce higher metal wiring aspect ratios, and more difficult feature fill for damascene processing. One method of extending the use of sputter deposition to challenging aspect ratios is to collimate the sputtered flux using a collimator plate, and to avoid randomizing the collimated flux by using low process pressures corresponding to long sputtered atom mean free paths. In this paper, we discuss our fabrication of damascene AI-0.5Cu-2Si and AI-2Mg wiring using both collimated and uncollimated sputtering, and our observations of collimation-induced changes in Al alloy electromigration and microstructure. Our experiments show that collimation has only a small effect on AlCuSi, but a large effect on AIMg. Specifically, the median time to electromigration failure for collimated AIMg was ∼10X the value for uncollimated AlMg and ∼6X the values for collimated and uncollimated AlCuSi. Transmission electron microscope and x-ray diffraction analyses of these films show that the collimation-induced improvement in AIMg t 50 is associated with the formation of smaller, lower strain grains which are clustered in very well-oriented (111) domains. We propose that the advantageous AlMg microstructure results from enhanced texture produced by aspects of the collimated deposition active in the absence of incoherent precipitates.

Stress-induced voiding in aluminum alloy metallizations

Fabrication of microelectronic metal interconnects generates a state of tensile stress in the metal. For constant metal and passivation film thicknesses, the magnitude of stress increases as linewidth decreases until the metal forms internal voids in order to relax. Such voids can grow large enough to sever lines, degrading chip functionality and reliability. For narrow lines, constraints from the passivation layer permit relaxation through void growth to occur only by diffusion. This phenom¬ enon is known as stress migration, by analogy to voiding produced by high electrical current (electromigration). To study the influence of alloy composition and microstructure on diffusion in Al-based interconnects with and without Ti underlayers, interconnects with different amounts of Si, Cu and oxygen were passivated with PECVD SiN, and aged at 150° C for 1000 hr in air. Samples were also electromigration-stressed to highlight possible interactive variables. AI-Cu produces fewer voids and longer electromigration lifetimes than pure Al. High (> 2%) Si appears to promote void formation by rapid grain boundary diffusion and precipitate growth, but does not necessarily decrease electromigration lifetime. Low Si (< 1%) appears to be beneficial for ex¬ tending electromigration lifetime and reducing the total volume of voiding, but causes large void sizes which lead to failure. The effect of oxygen contamination on stress migration is generally detrimental. Ti underlayers are redundant conductors which greatly increase electromigration life, but increase individual void size. A model for thermal dependence of atomic flux, used in con¬ junction with thermal stress hysteresis measurements of metal films, describes a wide range of voiding behavior.

Collimated sputtering of titanium liner films to control resistance of high-aspect-ratio contacts (Abstract Only)

Consistently low contact resistance is critical to performance and reliability of CMOS devices. Shrinking cell sizes have driven contact dimensions to increasingly higher aspect ratios. Previous technologies have used conventionally sputtered Ti/TiN contact liner films to provide good metallurgical bonding and electrical conductivity between silicide—clad diffusions and tungsten contact studs. However, for high aspect-ratio contacts, step coverage of conventional PVD Ti may not be adequate. It has bcen shown that step coverage may be enhanced through the use of a collimator. A collimator is a honeycomb-like device suspended between the target and wafer. This device screens sputtered species which travel in paths with angles of incidence non-normal to the wafer surface. This paper describes the development and evaluation of a 200 mm collimated titanium process for the IBM 16 Mb-DRAM. The 16-Mb device employs TiSi2-clad diffusions which are passivated with a doped glass. Contacts are patterned and etched through the glass to open the diffusions. The contact dimensions are nominally O.6-m in diameter by 1 .2-sm deep. Following etching, a Ti/TiN bilayer is deposited onto the wafer and CVD tungsten is deposited and planarized to form the contact stud. In the 16-Mb development program Ti coverage of the bottom of the contact was found to be critical to a robust process. Titanium is known to be highly reactive and is thought to consume native oxides and RIE residuals on the suicide surface. For contact dimensions currently under consideration, step coverage of conventional PVD films was typically < 10% . Step coverage of 15-40% has been demonstrated with collimation. Comparison of contact resistance data from wafers processed with collimated and conventionally deposited liner films shows a profound improvement with coffimation. Mean contact resistance for wafers with the conventional PVD liner process is typically greater than 100 ohms, with collimation, the resistance is typically less than 5 ohms. The presentation will also summarize a large database that has been generated on process stability, collimator lifetime and particulate performance.