Sergey V. Rylov

Josephson output interfaces for RSFQ circuits

We have developed and demonstrated high bandwidth Josephson circuits to interface the output of RSFQ circuits to room temperature electronics. Asynchronous dc powered voltage driver circuits have been designed to amplify RSFQ signal levels to voltage outputs in the 2-4 mV range, in a wide bandwidth. These driver circuits have been characterized and tested for data rates up to 8 Gb/s. The bit error rate for one of these drivers has been measured up to 7 Gb/s for a (2/sup 31/-1) bit long pseudo-random bit sequence (PRBS). In order to match the data rate of Josephson circuits to slower room temperature electronics, we have developed clock-controlled shift registers which allow shift-in and shift-out of data at different frequencies. Complete functionality of these circuits integrated with the drivers has been demonstrated at low speed. Shift registers integrated with the voltage driver circuits have been tested at high-speed for data rates up to 6 Gb/s.

Superconducting high-resolution A/D converter based on phase modulation and multichannel timing arbitration

We have developed a flux-quantizing A/D converter (ADC) based on RSFQ elements, employing a novel front end capable of generating high-linearity multibit differential code within a wide dynamic range (up to 16 bits). The front end operates as a phase modulator/demodulator and uses fractional-flux-quantum least significant bit (LSB). It runs at multi-GHz speed, enabling ADCs with large oversampling ratio and effective resolution in excess of 20 bits (after decimation filtering). We have designed, fabricated and tested several versions of a complete ADC using this new architecture and demonstrated its operation with dynamic range of 14 bits. We have also confirmed continuous phase modulation of the flux quantizer with a carrier frequency of 10 GHz.<<ETX>>

A superconductive flash digitizer with on-chip memory

Recording transient physical phenomena such as short electromagnetic pulses requires a very wide-band digitizer. We have successfully designed, fabricated, and tested a superconductive flash digitizer circuit using Nb trilayer technology. The digitizer consists of a 6-bit flash analog-to-digital converter (ADC), a set of on-chip switches to start and stop data acquisition, and a bank of acquisition shift-registers for on-chip memory. A 5-MHz clock reads the data out to room-temperature electronics for analysis. We have used this digitizer to acquire multi-GHz sine waves. We have also recorded the details of short single pulses containing both a short rise time (/spl sim/100 ps) and structure with greater than a 10 GHz instantaneous bandwidth.

Progress in Design of Improved High Dynamic Range Analog-to-Digital Converters

We describe several improvements that are being pursued to improve the dynamic range of lowpass phase modulation-demodulation (PMD) analog-to-digital converters (ADC). The existing ADC has been tested at sampling frequencies up to 29.44 GHz; a 89.15 dB signal to noise ratio (SNR) is achieved for a 10 MHz sinusoidal input, with the noise being measured in a reference 10 MHz bandwidth in the decimated band. The first improved approach involves a multi-rate ADC where the modulator sampling frequency is increased in multiples of the decimation filter clock. We have tested the multi-rate ADCs at sampling frequencies up to 46.08 GHz and 29.44 GHz for chips fabricated using the 4.5 and 1 kA/cm2 fabrication processes respectively. For a single channel ADC, with a 9.92 MHz sinusoidal input, sampled at 29.44 GHz, the SNR is 83.93 dB in a reference 10 MHz bandwidth. The spur-free dynamic range (SFDR) is 95 dB. In another improved architecture, called the quarter-rate ADC, the modified quantizer quadruples the input dynamic range by distributing the input in a cyclical fashion to four output channels, each operating at a quarter of the fluxon transport rate. This enables quadrupling the synchronizer channels, providing an opportunity for up to 12 dB performance enhancement. A parallel counter following the multi-channel synchronizer converts the differential code to a multi-bit binary code, which is further processed by the decimation filter. A prototype version of this ADC with a two channel synchronizer, fabricated using the 4.5 kA/cm2 process, has been tested up to a sampling frequency of 25.6 GHz. For a 10 MHz sinusoidal input, the SNR is 82.54 dB, with the noise measured in a reference 10 MHz bandwidth. We are also designing a subranging ADC with two PMD front-ends. Simulation results promise greater than 20 dB performance enhancement.

High resolution ADC system

We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology.

Superconducting Switching Amplifiers for High Speed Digital Data Links

In a superconductor digital-RF transmitter, the power amplifier chain can be implemented in hybrid temperature, hybrid technology environment, where the superconductor switching amplifier forms the first stage of the amplification chain. We have designed several flavors of SQUID based switching amplifiers, each targeted for different power output and speed. One of the amplifiers is a differential amplifier featuring dynamic equalization. To minimize the intersymbol interference, the amplifier employs a pre-emphasis technique, thereby compensating for the bandwidth limitations of the channel. The differential output voltage of this amplifier is 16 mV at low speed (200 Mbps), which rolls off to 2 mV at 16 Gbps data rate, for an ldquo1100rdquo pattern (no consecutive transitions on the input data sequence). For high speed operation of the SQUID amplifiers, simultaneous switching of SQUIDs is desired to reduce the output rise and fall times. Hence, in another amplifier design, called the Differential H-Tree Amplifier, the SQUIDs are arranged in an ldquoH-treerdquo structure, to equalize the propagation delay of the control signal to each SQUID. The amplifiers differential output voltage is 8 mV at low speed (200 Mbps), and rolls off to 2 mV at 10 Gbps data rate. A third type of amplifier is a differential SFQ-to-DC amplifier; it consists of a pair of synchronously driven SFQ-to-DC converters that produce complementary positive and negative voltage waveforms respectively. The differential output voltage of this amplifier is 0.8 mV, and it can be operated at very high speeds. Moreover, the complexity of this amplifier enables it to be yielded in higher critical current density process. Both, the speed and the output voltage scale as the square root of the process critical current density.

A comparison of two types of single flux quantum comparators for a flash ADC with 10 GHz input bandwidth

We compare the SQUID wheel/Quantum Flux Parametron (QFP) comparator to a new Rapid Single Flux Quantum (RSFQ) compatible design. Both have been simulated to demonstrate /spl sim/0.5 ps threshold accuracy which would permit the construction of a flash analog-to-digital converter with six effective bits of resolution at 10 GHz input bandwidth, over three times better than the best performance demonstrated with any technology, At lower input frequencies, both designs have demonstrated that a 10-bit flash ADC is possible. Although simulations of the QFP-based design are more accurate at high signal slew rates due to its symmetry, the RSFQ-based design has a better signal-to-noise ratio and a faster and more flexible clocking scheme which ultimately prove to be more important.

An experimental digital SQUID with large dynamic range and low noise

A digital SQUID chip designed for large dynamic range and intrinsic sensitivity as good as an analog SQUID was fabricated and tested. It consists of a pickup coil, a SQUID amplifier, edge-triggered latching comparators, and a feedback loop using an integrating single-flux-quantum D/A converter. Proper operation of the chip was demonstrated, with the output one-bit data stream averaged and integrated to reconstruct the input signal. A sampling rate up to 500 MHz was achieved.<<ETX>>

An integrated digital SQUID magnetometer with high sensitivity input

A single chip SQUID magnetometer is described that integrates a SQUID-based pre-amplifier with a high sensitivity comparator gate and feedback circuitries on the same chip. The comparator gate is an asymmetric SQUID gate driving two SQUID quantizers in series with the feedback coil. The chips sensitivity and noise level are primarily determined by the pre-amplifier SQUID. The pick up coil is in series with the feedback transformer. Since the current in the feedback coil is maintained close to zero, the dynamic range of the chip can be extremely wide and is independent of the SQUID pre-amplifier or comparator architectures. The chips slew rate is determined by the bipolar clock biasing the comparator gate. Clocks running in the tens of MHz result in a magnetometer system with slew rate exceeding 10/sup 5/ /spl Phi//sub 0//s (/spl Phi//sub 0/=2.07/spl times/10/sup -7/ Gauss-cm/sup 2/). This chip simplifies room temperature electronics and, due to its digital output, can be easily multiplexed on-chip. A system based on this chip can be operated in a relatively high magnetic field environment without extensive magnetic shielding. The details of the chip as well as preliminary measurement results for the pre-amplifier as well as the digital circuit will be presented.<<ETX>>

Measurements of dynamic range and linearity of flux-quantizing A/D converters

High-precision measurements of the linearity of a flux-quantizing analog-to-digital converter (ADC) using a pair of 6-b rapid single-flux-quantum (RSFQ) counters have been made. The sensitivity and dynamic range of the ADC were 13.3 mu A/least significant bit (LSB) and +or-30 mA, respectively (12 b). The conversion curve was measured with an accuracy of +or-7.5% of LSB within a dynamic range of 9 b and exhibited no evidence of nonlinearity. In addition, tests have been made on stand-alone flux quantizers with dynamic range up to 16 b, and a unidirectional 12-b ADC which directly demonstrated a correct divide-by-2/sup 12/ operation with a 10-GHz, 4 LSBs sinewave input signal (peak counting frequency in excess of 80 GHz).<<ETX>>