Alexander V. Rylyakov

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

A 71-Gb/s NRZ Modulated 850-nm VCSEL-Based Optical Link

We report error free (BER <; 10-12) operation of a directly non-return-to-zero modulated 850-nm vertical cavity surface-emitting laser (VCSEL) link operating to 71 Gb/s. This is the highest error free modulation rate for a directly modulated laser of any type. The optical link consists of a 130-nm BiCMOS driver IC with two-tap feed-forward equalization, a wide bandwidth 850-nm VCSEL, a surface illuminated GaAs PIN photodiode, and a 130-nm BiCMOS receiver IC.

A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

Monolithic Silicon Integration of Scaled Photonic Switch Fabrics, CMOS Logic, and Device Driver Circuits

We demonstrate 4 × 4 and 8 × 8 switch fabrics in multistage topologies based on 2 × 2 Mach-Zehnder interferometer switching elements. These fabrics are integrated onto a single chip with digital CMOS logic, device drivers, thermo-optic phase tuners, and electro-optic phase modulators using IBMs 90 nm silicon integrated nanophotonics technology. We show that the various switch-and-driver systems are capable of delivering nanosecond-scale reconfiguration times, low crosstalk, compact footprints, low power dissipations, and broad spectral bandwidths. Moreover, we validate the dynamic reconfigurability of the switch fabric changing the state of the fabric using time slots with sub-100-ns durations. We further verify the integrity of high-speed data transfers under such dynamic operation. This chip-scale switching system technology may provide a compelling solution to replace some routing functionality currently implemented as bandwidth- and power-limited electronic switch chips in high-performance computing systems.

40 Gbit/sec circuits built from a 120 GHz f/sub T/ SiGe technology

Product designs for 40 Gbit/sec applications fabricated from SiGe BiCMOS technologies are now becoming available. This paper will briefly discuss technology aspects relating to HBT device operation at high speed, acting to dispel some common misconceptions regarding SiGe HBT technology applicability to 40 Gbit/sec circuits. The high speed portions of the 40 Gbit/sec system are then addressed individually, demonstrating substantial results toward product offerings, on each of the critical high speed elements.

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.

CMOS-Integrated Optical Receivers for On-Chip Interconnects

This paper reviews recent progress on CMOS-integrated optical receivers for on-chip interconnects, which have become attractive for achieving communication bandwidth well beyond terabit-per-second with low-power consumption. The design of optical receivers and the performance metrics required from the photodetector (PD) for a low-power receiver is discussed. The progress in waveguide-integrated germanium PDs is reviewed in depth by exploring various optical/electrical designs, and the associated integration approaches for Ge films and metal contacts. The impact of design and integration on PD performance is evaluated by comparing reported results. Finally, the challenges of monolithic integration of PDs within standard CMOS process are discussed.

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are packaged to enable bit-error-rate testing by connecting their serial interfaces. Operation is error-free for both circuits at data rates >50 Gb/s and -3.6 V supply.

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

A 24-Channel, 300 Gb/s, 8.2 pJ/bit, Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single “Holey” CMOS IC

We report here on the design, fabrication, and high-speed performance of a compact 48-channel optical transceiver module enabled by a key novel component: a “holey” Optochip. A single CMOS transceiver chip with 24 receiver (RX) and 24 laser diode driver circuits, measuring 5.2 mm × 5.8 mm, becomes a holey Optochip with the fabrication of forty-eight through-substrate optical vias (holes): one for each transmitter (TX) and RX channel. Twenty-four channel, 850-nm VCSEL and photodiode arrays are directly flip-chip soldered to the Optochip with their active devices centered on the optical vias such that optical I/O is accessed through the substrate of the CMOS IC. The holey Optochip approach offers numerous advantages: 1) full compatibility with top emitting/detecting 850-nm VCSELs/PDs that are currently produced in high volumes; 2) close integration of the VCSEL/PD devices with their drive electronics for optimized high-speed performance; 3) a small-footprint, chip-scale package that minimizes CMOS die cost while maximizing transceiver packing density; 4) direct coupling to standard 4 × 12 multimode fiber arrays through a 2-lens optical system; and 5) straightforward scaling to larger 2-D arrays of TX and RX channels. Complete transceiver modules, or holey Optomodules, have been produced by flip-chip soldering assembled Optochips to high-density, high-speed organic carriers. A pluggable connector soldered to the bottom of the Optomodule provides all module electrical I/O. The Optomodule footprint, dictated by the 1-mm connector pitch, is 21 mm × 21 mm. Fully functional holey Optomodules with 24 TX and 24 RX channels operate up to 12.5 Gb/s/ch achieving efficiencies (including both TX and RX) of 8.2 pJ/bit. The aggregate 300-Gb/s bi-directional data rate is the highest ever reported for single-chip transceiver modules.