John G. Kauffman

An 8.5 mW Continuous-Time

This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the ΔΣ modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are compensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The presented ΔΣ modulator has been realized in a 1.2 V, 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 mm2 and has a power consumption of 8 mW, with an additional 0.02 mm2 and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv.

\Delta \Sigma

This paper presents a single loop, third order continuous time ΔΣ modulator with an internal 4 bit quantizer sampled at 500 MHz with only an oversampling ratio of 10. Since multi-bit operation commonly suffers from DAC non-linearities, and dynamic element matching is ineffective at low oversampling, an alternative auxiliary DAC linearization is proposed for ΔΣ modulators. The unit element mismatches are digitally estimated based on a cross correlation of a binary test signal with the modulator output and represent the measured DNL of DAC1. The corresponding INL is calculated and stored in an 15×8 lookup-table which is applied to the 8 bit auxiliary DAC to linearize DAC1. Moreover, a design centering approach for amplifier finite gain bandwidth compensation within the loop filter is presented which allows for large bandwidth mismatch with negligible effect on loop filter stability. This results in a robust architecture over temperature, supply, and excess loop delay variations. The presented ΔΣ modulator achieves an SNDR of 67.5 dB, DR of 72 dB, and SFDR of 79 dB over a 25 MHz bandwidth and is implemented in a 1.2 V, 90 nm CMOS process. The modulator occupies an active area of 0.19 mm2 and has a power consumption of 8.5 mW. It achieves a figure of merit of 88 fJ/conv-step which is one of the best published for multi-bit ΔΣ modulators.

Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR

There is ongoing effort to realize low-power ΔΣ ADCs with more than 10MHz bandwidth (BW) — especially for wireless transceivers. Besides the trend to make these ADCs more reconfigurable [1], recent advances in the design of CT ΔΣ modulators focused on design improvements [2], on replacing analog by digital circuits [3, 4], or on avoiding costly multi-bit DACs with time-domain or singlebit feedback [1, 4]. Apart from that, the power versus performance advances in ΔΣ ADCs have slowed down, and the best FOM for above 10MHz ΔΣ modulators (ΔΣMs) is still 120fJ/conv [5]. Among other reasons, the further advance of ΔΣMs to higher conversion BWs with compatible FOM faces two hurdles: first, high BW requires a low OSR to achieve a feasible sampling frequency fS. Since the filter order rarely exceeds three, multi-bit operation is commonly employed. This requires linearization of the multilevel feedback DAC, e.g., by using DEM, which is however ineffective at low OSR [6]. Therefore, a large, linear multilevel DAC is needed, which introduces a significant parasitic load for the amplifiers and increases their power consumption. Proposed time domain multi-bit DACs still worsen the jitter sensitivity [4]. Second, the operation at high fS makes the excess loop-delay (ELD) a large fraction of the sampling period. This ELD is caused by the quantizer, the phase shift due to finite amplifier BW [1][2], and the DEM. While many different techniques for ELD compensation have been proposed, the basic idea remains to realize a fast feedback loop around the quantizer. Alternative implementations with a summer, integrators with differentiating DAC [5], or compensation within the quantizer [1] only change the required location of the fast settling speed and high power. When implemented with the last integrator, ELD compensation makes its speed requirements the highest within the ΔΣ loop filter [1].

A 72 dB DR, CT Delta Sigma Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

The ongoing trend for wide-band, power-efficient continuous-time ΔΣ modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3rd or 4th-order loop-filters [1,2]. In order to improve power efficiency, circuit and architectural innovations [1], as well as digital implementation [3] or digital correction of analog circuit parts have been used. To date, the best power vs. performance ratio for ΔΣ modulators with above 10MHz bandwidth is held by [1] with an FoM of 120fJ/conv.

An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization

This paper presents a continuous-time third-order low-pass delta-sigma modulator (DSM) with digitally enhanced out-of-band (OOB) signal filtering for enhanced blocker rejection in receiver analog-to-digital converters (ADCs). It is well known that strong OOB interferers define the required dynamic range (DR) of a receiver. Usually, a channel-select filter (CSF) is therefore required, together with the succeeding ADC. The feedback-compensated DSM can relax the CSF with its signal transfer characteristic. In this work, this is improved with a reconfigurable digital filter, which modifies the feedback signal of the outer-loop DAC to increase the OOB blocker rejection of the modulator. As a proof of concept, the digitally improved blocker rejection is shown in a prototype design. Additionally, a reconfigurable excess loop delay compensation technique based on an adaptive delay-locked-loop (DLL) has been implemented. The prototype is realized in a 90 nm CMOS technology, works at 480 MHz clock frequency, requires an area of 0.17 mm2, and achieves an in-band (IB) SNDR of 70 dB in a bandwidth of 10 MHz with a power consumption less than 14.4 mW. In the prototype, a digitally reconfigurable blocker rejection is realized achieving 6 dB additional suppression from 20 or 40 MHz on, or even 25 dB at the specific frequency of 20 MHz.

A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

This brief presents a background digital-to-analog converter (DAC) error estimation technique for multibit bandpass Delta-Sigma analog-to-digital converters (ΔΣ ADCs). The technique is used to estimate and linearize the intrinsic mismatches of feedback DAC unit elements of ΔΣ ADCs. It consists of three building blocks, namely, a correlation-based error estimation, which utilizes a test signal to estimate DAC unit element gain mis matches; a digital error correction, which corrects the estimated DAC nonlinearities; and a unit establishing background operation. The method has been successfully utilized for lowpass ΔΣ ADCs and is extended here by using an additional bandpass filter to create a modified test signal, which meets the requirements of bandpass Δ modulators. The method restores highly nonlinear systems back to their ideal linearity while requiring only little additional hardware effort and enables the design of linear multibit bandpass ΔΣ modulators.

A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection

This paper presents a third order continuous time Delta Sigma modulator with a 4 bit internal quantizer sampling at 1GHz using an oversampling ratio of 10. Since dynamic element matching is ineffective at low oversampling and difficult to design within the loop at high sampling rates, a DAC linearization can be used in the digital domain to correct for non-linearities of DAC1. The presented modulator has been realized in a 1.2V, 90nm CMOS process and achieves an SNDR of 61.7 dB, DR of 67dB and an SFDR of 72dB within a 50MHz bandwidth. Overall, the modulator achieves a figure of merit of 207 fJ/conv.

A Correlation-Based Background Error Estimation Technique for Bandpass Delta–Sigma ADC DACs

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.

A 67dB DR 50MHz BW CT Delta Sigma modulator achieving 207 fJ/conv

This paper presents the design of an fully differential current steering DAC for a continuous time (CT) ΔΣ modulators with an all native switched DAC cell. In using the proposed cell a lower load capacitance on the virtual ground node of the integrator, reduced charge injection and clock feed-through is obtained when compared to the commonly used NMOS/PMOS DAC cell, thus resulting in an improved performance and lower ISI sensitivity. The native switched DAC is functionally demonstrated within a third order CT ΔΣ modulator operating at an fS of 1GHz with an OSR of 20. The schematic based DAC is designed in a 1.2V 90nm TMSC process including V-I biasing to track the modulator input resistance. Within the explemary ΔΣ modulator an SNDR of 79.12dB and SFDR of 93.44dB within a 25MHz bandwidth is achieved while only being limited by the thermal input noise of the modulator. When comparing to the commonly used NMOS/PMOS switched cell, an improvement of 3dB and 7.3dB in SNDR and SFDR is achieved with the same area and current.

Analysis and design of high speed/high linearity continuous time delta-sigma modulator

This paper describes a method to improve the linearity, area or SNR of feedback (FB) compensated Sigma-Delta (ΣΔ) modulators. These performance limiting factors are often related to the outer loop feedback DAC or to the 1st integrator of the ΣΔ-modulator in a FB-compensated modulator. This work focuses on improvements of the 1st integrator. The origin of these problems is the output swing of the 1st integrator, which includes and is dominated by the input signal. This problem is usually solved by increasing the capacitor size of this integrator, which results in an increased area and power. Another common solution is to use a feed-forward (FF) compensated ΣΔ-modulator, where basically only quantization noise is processed by the 1st integrator. However the drawback of this approach is a usually wide bandwidth and peaking of the modulators signal transfer function (STF). The proposed solution greatly reduces signal swing at the 1st integrator, by not affecting the STF. Thus, it takes the advantages of the FF-topology, by keeping the advantages of the FB-topology.