Timon Brückner

Concurrent estimation of amplifier nonidealities and excess loop delay in continuous-time sigma-delta modulators

In this work, a method for the concurrent estimation of nonidealities in continuous-time sigma-delta modulators is presented. Several nonidealities can degrade the performance of a sigma-delta modulator, even up to instability of the entire circuit. However, if these nonidealities are known, it is possible to correct for most of them - either in the analog or digital domain. In the past, many techniques for corrections of errors in sigma-delta modulators have been presented. Although these works show good results, most are only able to work on a single or few nonidealities simultaneously. In this paper, a feasible approach for estimating several nonidealities in a joint fashion has been applied to estimate some of the most prominent errors in a continuous-time sigma-delta modulator.

Calculating transfer functions of CT sigma-delta modulators with arbitrary DAC waveforms

In this paper, a new method of calculating the transfer functions of continuous-time (CT) sigma-delta modulators is presented. The common approach of calculating the transfer functions is to analyze a discrete-time (DT) equivalent of the CT loop filter together with the CT input filter path. The DT equivalent is most commonly obtained via either the impulse invariant or the modified Z-transformation. This work provides a numerical alternative to these methods, based on DT simulation models, which can be obtained by a previously published method of DT simulating CT sigma-delta modulators, called lifting. This allows incorporating all linear-time-invariant non-idealities, such as finite DC gains and gain-bandwidths in the integrator stages, as well as excess-loop-delay and any waveform shape in the digital-to-analog converter.

A novel optimization method for CT sigma-delta-modulators using a switched system model

This paper presents an approach to analyse the stability of continuous time ΣΔ data converters and shows a new method to define optimized parameter sets without a large number of simulations. Thereby the converter is described as a switched system. The presented analysis is based on a state space description which is utilized to express the properties of a stable behaviour. It is shown how the analysis method can be used to optimize the filter coefficients of the modulator by scaling the integrators outputs

STF optimization of 1-bit CT ΣΔ modulators based on scaled loop filter coefficients

This paper presents how the optimization of continuous-time (CT) ΣΔ modulators by scaling the loop filter coefficients affects the signal transfer function (STF) and in which way the method can be used to reduce peaking in the STF. It is shown that, depending on the initial design, it is possible to define optimized parameter sets with increased performance and remaining flat STF or sets with constant performance and reduced STF peaking. Therefore, the system is first described as switched system to analyse its behaviour in the state space. The different effects of the optimization method on the STF are demonstrated on two example systems with differently designed noise transfer functions (NTF).

Design of a current steering DAC for a high speed current mode SAR ADC

In this paper, an approach towards high speed current mode based SAR ADCs is presented. The main focus is placed on the design of a unary single-sided current steering DAC working with a binary search algorithm inside the SAR loop. Reflecting the fact that current source matching and precise current settling are the most important static and dynamic properties of the current steering DAC in a current based SAR ADC, the paper contains an initial investigation of the DAC current settling when driving a linear load together with an analysis of the effects of current source mismatch and noise on the DAC performance. The theoretical analysis is compared against a schematic level implementation in a 1.2V 90nm CMOS technology. This DAC implementation is designed for an overall resolution of 10bit in the current based SAR ADC over a Nyquist band from DC to 100MHz.

Discrete-time simulation of arbitrary digital/analog converter waveforms in continuous-time sigma-delta modulators

In this paper, the inclusion of arbitrary feedback pulses into the method of discrete-time simulation of continuous-time sigma-delta modulator is investigated. Although rectangular feedback pulses cover the majority of the published sigma-delta modulator circuits, there arise well known advantages from other waveform shapes, such as reduced sensitivity to excess-loop-delay in the feedback path, finite gain bandwidths in the operational amplifiers and clock-jitter. In order to also utilize the benefit of fast discrete-time simulations of continuous-time modulators in the case of non-rectangular digital-to-analog converter waveforms, this work provides the mathematical background for accurate modeling. Comparative simulations show a speed advantage of up to more than three order of magnitude.

A square root unscented Kalman filter for estimating DAC and loopfilter nonidealities in continuous-time sigma-delta modulators

In this work, an unscented Kalman filter with improved numerical properties is shown to be able to simultaneously estimate the major nonidealities of continuous-time sigma-delta modulators. Circuit imperfections in sigma-delta modulators like, e.g., nonlinearities in the feedback digital-to-analog converters are known to highly reduce the modulatorss performance. The state of the art shows several techniques to compensate for some of these nonidealities, whereby most of the methods only focus on single parameters or can only be applied to specific modulator structures. The presented method is capable of estimating the most serious nonideal circuit parameters concurrently whilst not being limited to specific modulator structures.

Analysis and design of high speed/high linearity continuous time delta-sigma modulator

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.

PVT robust design of wideband CT delta sigma modulators including finite GBW compensation

This paper demonstrates the effectiveness and robustness of amplifier finite gain bandwidth compensation within a wideband third order continuous time delta sigma modulator and the effects of process, mismatch and temperature on modulator stability. In many state of the art designs, GBW is kept safely above the sampling frequency of the modulator, which suffers a power penalty especially for high-speed designs. While gain errors and phase shifts in the loop filter due to finite GBW can be compensated for, its robustness is often questionable, especially if an additional excess loop delay is concerned. The robustness of such a compensation is analyzed for an exemplary CT DSM with an fS of 500MHz which has been designed in a 1.2V 90nm TSMC CMOS process. Therefore, the amplifiers are compensated for finite GBW values of 500 MHz, 300MHz and 600 MHz, and all three parasitic extracted amplifiers are analyzed over PVT. The simulated modulator performance of 72 dB SNDR over a 25MHz bandwidth is only degraded by 2 dB over corner simulations. In comparison to Monte Carlo analysis of all amplifiers, this reveals a modulator robustness to amplifier finite GBW as much as ±35% over process and mismatch, which emphasizes the feasibility of the approach.

Automated Design of High-Speed CT ΣΔ Modulators Employing Compensation and Correction of Non-idealities

In this contribution, we discuss our recent advances in the automated design of continuous-time sigma-delta modulators. In the state of the art, the architectural and circuit level design of these modulators, especially if high-speed, low power or high resolution is targeted, either requires broad experience in the loop filter design, or relies on mathematical transformations which does not include the influence of non-idealities nor gives control about the signal transfer function, or the design is based on a very time consuming, massive simulation approach. Our solution is based on a detailed high level modeling, which allows to include many of the common non-idealities into the architectural design. By using an exact DT simulation of the CT modulator, and by employing a GPU-based heuristic search, a quasi real-time design optimization is obtained. The adoption of this tool, which is online available via a web page, is shown for the design of a 50 MHz, 10 bit sigma-delta modulator.