John M. Lannon

High density interconnect at 10µm pitch with mechanically keyed Cu/Sn-Cu and Cu-Cu bonding for 3-D integration

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10µm and 15µm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99% individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 23 consecutive bond pairs was made with mechanical key, resulting in 92% aggregate channel yield at 10µm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The effects of thermal cycling on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made.

Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration

The use of collapsible (solder) bump interconnects in pixel detector hybridization has been shown to be very successful. However, as pixel sizes decrease, the use of non-collapsible metal-to-metal bump bonding methods is needed to push the interconnect dimensions smaller. Furthermore, these interconnects are compatible with 3D intgration technologies which are being considered to increase overall pixel and system performance. These metal-to-metal bonding structures provide robust mechanical and electrical connections and allow for a dramatic increase in pixel density. Of particular interest are Cu-Cu thermocompression bonding and Cu/Sn-Cu solid-liquid diffusion bonding processes. Working with Fermilab, RTI undertook a demonstration to show that these bump structures could be reliably used to interconnect devices designed with 20 micron I/O pitch. Cu and Cu/Sn bump fabrication processes were developed to provide a well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. The electrical resistance and yield has been quantified based on electrical measurements of daisy chain test structures and the mechanical strength of the bonding has been quantified through die shear testing. The reliability has been characterized through studies of the impact of thermal exposure on the mechanical performance of the bonds. Cross-section SEM analysis, coupled with high resolution energy dispersive spectroscopy, has provided insight into the physical and chemical nature of the bonding interfaces and aided in the evaluation of the long-term stability of the bonds.

High Density Metal–Metal Interconnect Bonding for 3-D Integration

3-D integration provides a pathway to achieve high performance microsystems through bonding and interconnection of best-of-breed materials and devices. Bonding of device layers can be accomplished by dielectric bonding and/or metal-metal interconnect bonding with a number of metal-metal systems currently under development. RTI has been investigating Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications. The interconnect pad fabrication processes and the interconnect bonding conditions (pressure and temperature) required for the formation of low resistance (10s of mΩ), high yielding (≥99.98% bond yield), and reliable interconnects are described. The effects of thermal reliability testing (aging) on electrical connectivity and mechanical strength are presented. Results from the two metal-metal interconnect bonding systems are compared in terms of ease of assembly and small pitch (sub-15 μm ) scaling. Methods for obtaining high bond yield at smaller pitches are discussed.

Bonding for 3-D Integration of Heterogeneous Technologies and Materials

Modern electronic applications demand more and more complex, multifunctional microsystems with performance characteristics which can only be achieved by using best-of-breed materials and device technologies. Three-dimensional (3-D) integration of separate, individually complete device layers provides a way to build complex heterogeneous microsystems without compromising the system performance and fabrication yield. In the 3-D integration approach, each device layer is fabricated separately using optimized materials and processes. The layers are bonded and interconnected through area array vertical interconnects with lengths on the order of microns. This paper will review bonding techniques for high density area array 3-D integration of integrated circuits, focusing on techniques suitable for die-to-die and die-to-wafer bonding configurations.

High density Cu-Cu interconnect bonding for 3-D integration

The demand for more complex and multifunctional microsystems with enhanced performance characteristics is driving the electronics industry toward the use of best-of-breed materials and device technologies. Three-dimensional (3-D) integration enables building such high performance microsystems through bonding and interconnection of individually optimized device layers. Bonding of device layers can be achieved through polymer bonding or metal-metal interconnect bonding with a number of metal-metal systems (e.g. Cu-Cu, Cu/Sn-Cu, etc.) currently under development. RTI has been investigating and characterizing Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications, demonstrating bonding between pads less than 15 microns in diameter for large area array configurations. Cu and Cu/Sn bump fabrication processes were developed that provide well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. In this paper, the effects of Cu interconnect bonding parameters (pressure and temperature) and thermal reliability testing (thermal cycling and aging) on electrical connectivity and mechanical strength are presented and compared to Cu/Sn-Cu interconnect bonding with an eye toward small pitch scaling and ease of assembly. The conditions for producing Cu-Cu bond strengths ≫ 110 MPa and electrical connectivity as high as 99.999% are described.

Reliability and ultra-low temperature bonding of high density large area arrays with Cu/Sn-Cu interconnects for 3D integration

The results of lifetime testing of Cu/Sn-Cu eutectic bonded dice at 10µm pitch in large area arrays of 325,632 interconnects are shown. The interconnect bonding process (pressure and temperature) required for the formation of low resistance (∼100 mΩ), high yielding (99.99% individual bond yield), and reliable interconnects is described. The effects of thermal cycling on electrical yield and resistance are presented. Ultra-low temperature eutectic bonding (at 210°C, below the melting point of tin) is demonstrated to produce high electrical yield, high shear strength and similar intermetallic compound formation to devices bonded at the standard 300°C temperature. Electrical results, shear test results, SEM cross sections and EDS analysis comparisons are presented. The ultralow temperature process may prove useful for integrating IC dice that have low thermal budgets.

Fabrication and testing of thin silicon interposers with multilevel frontside and backside metallization and Cu-filled TSVs

Thin silicon or glass interposers provide a path to highly integrated microsystems. In this work we present a process for the fabrication and bonding of 100 and 200 μm thick silicon interposers with frontside and backside multilevel metal (MLM) routing layers and copper filled through-silicon vias (TSVs) with the aspect ratio of 4:1. First, we show the results of a study done to evaluate the compatibility of two types of temporary wafer bonding systems with the deposition, patterning, and cure of three different spin-on dielectric polymers used in the MLM structures. This study also examines bonding of the interposer die to a substrate and the removal of the supporting carrier. Secondly, we describe the process for the fabrication of the Si interposers and present results of electrical testing. Electrical testing before and after thermal cycling revealed a greater than 99% yield of TSVs and a high level of electrical isolation between TSVs. In this paper we demonstrate that a silicon interposer fabrication process using the combination of polymer dielectrics, plated copper routing lines, copper TSVs, and temporary wafer bonding can produce high yielding and robust structures.

Process integration and testing of TSV Si interposers for 3D integration applications

Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules. The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6” wafers. The front-side MLM was comprised of 4 metal routing layers (2 μm Cu with 2 μm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was <; 4 MΩ per via. TSV dimensions of 100 and 80 μm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 MΩ and sufficient TSV isolation resistance (>;100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm × 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), wafer-level packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6” wafers. Via dimensions for the viasfirst interposers were 50 μm diameter × 315 μm depth or 80 μm diameter × 315 μm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 μm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.

MIRAGE: developments in IRSP system development, RIIC design, emitter fabrication, and performance

Santa Barbara Infrareds (SBIR) family of MIRAGE infrared scene projection systems is undergoing significant growth and expansion. The first lot of production IR emitters is in fabrication at Microelectronics Center of North Carolina/Research and Development Institute (MCNC-RDI), the state-of-the-art MEMS foundry and R&D center which completed prototype fabrication in early 2003. The latest emitter arrays are being produced in support of programs such as Large Format Resistive Array (LFRA) and MIRAGE 1.5, MIRAGE II, and OASIS. The goal of these new development programs is to increase maximum scene temperature, decrease radiance rise time, support cryogenic operation, and improve operability and yield. After having completed an extremely successful prototype run in 2003, SBIR and MCNC-RDI have implemented a variety of emitter process improvements aimed at maximizing performance and process yield. SBIR has also completed development and integration of the next-generation MIRAGE command and control electronics (C&CE), an upgraded calibration radiometry system (CRS), and has developed test equipment and facilities for use in MIRAGE device wafer probing, test, evaluation, diagnostic, and assembly processes. We present the latest emitter performance data, an overview of emitter foundry processing and packaging improvements, and an update on MIRAGE II, LFRA, and OASIS development programs.

Coexistence of glassy antiferromagnetism and giant magnetoresistance in Fe/Cr multilayer structures

Abstract Using temperature-dependent magnetoresistance and magnetization measurements on Fe/Cr multilayers that exhibit pronounced giant magnetoresistance (GMR), we have found evidence for the presence of a glassy antiferromagnetic phase. This phase reflects the influence of interlayer exchange coupling (IEC) at low temperature ( T K ) and is characterized by a field-independent glassy transition temperature, T g , together with irreversible behavior having logarithmic time dependence below a “de Almeida and Thouless” critical field line. At room temperature, where the GMR effect is still robust, IEC plays only a minor role, and it is the random potential variations acting on the magnetic domains that are responsible for the antiparallel interlayer domain alignment.