Dorota Temple
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Featured researches published by Dorota Temple.
Applied Physics Letters | 2004
Jay Lewis; Sonia Grego; Babu R. Chalamala; Erik Vick; Dorota Temple
Multilayer indium-tin-oxide (ITO)–Ag–ITO stacks were evaluated as transparent conductors for flexible organic light-emitting diode (OLED) displays. The ITO–metal–ITO (IMI) samples exhibited significantly reduced sheet resistance over ITO and greater than 80% optical transmission. The IMI films deposited on plastic substrates showed dramatically improved mechanical properties when subjected to bending both as a function of radius of curvature as well as number of cycles to a fixed radius. OLEDs were fabricated on both ITO and IMI anodes, and the devices with IMI anodes showed improved performance at current densities greater than 1mA∕cm2 due to the improved conductivity of the anode.
Materials Science & Engineering R-reports | 1999
Dorota Temple
This article discusses the current status of the rapidly evolving area of field emitter arrays. The development of field emitter arrays is reviewed in the context of major applications of the devices, such as flat panel displays and cathodes for microwave power amplifiers. State-of-the art technologies for fabrication of field emitter arrays as well as recently reported results on electrical performance of the devices are reviewed. Remaining challenges in the major applications in conjunction with some of the potential pathways to device improvement are discussed.
Journal of The Electrochemical Society | 1989
Dorota Temple; A. Reisman
Thermally activated decomposition of the vapor phase of copper (II) hexafluoroacetylacetonate was studied
Applied Physics Letters | 1995
O. Auciello; M Ray; D Palmer; J Duarte; G.E. McGuire; Dorota Temple
Electron emission from ferroelectric thin films (≤1 μm thick) is demonstrated. In addition, electron energy distributions have been measured using an Auger electron spectrometer. The electron emission measurements were performed using ferroelectric cathodes based on this Pb(Zr0.53Ti0.47)O3 (PZT) films and 80–110 μm Pb0.93La0.07(Z0.53Ti0.47)O3 (PLZT) layered capacitors with Pt top and bottom electrodes. Current densities in the range of 0.5–1.5 mA/cm2 were measured from the PLZT cathodes excited with 100–400 V pulses, which produced electrons of about 265 eV with a narrow energy distribution (full width at half‐maximum of about 30 eV). On the other hand, current densities in the range 0.07–0.15 μA/cm2 were measured for thin film PZT‐based cathodes excited with pulses in the range 10–40 V. The initial results suggest that the electron emission current may depend, among other factors, on the thickness of the ferroelectric layer, the applied excitation voltage, and the interval between the polarizing and swit...
Journal of The Society for Information Display | 2005
Sonia Grego; John Lewis; Erik Vick; Dorota Temple
Abstract— Two different approaches to automated bend testing of flexible substrates for display applications were implemented and characterized: a conventional collapsing radius geometry and a novel technique called the “X-Y-θ” geometry. Indium tin oxide (ITO) coated polymer substrates were used to compare the performance of the two automated systems by in-situ electrical-resistance measurements. Manual bending on fixed-diameter mandrels was used to help interpret the results. The advantages and drawbacks of the two systems for providing information of practical use to flexible display R&D are discussed.
electronic components and technology conference | 2006
Christopher Bower; Dean Malta; Dorota Temple; J.E. Robinson; P.R. Coffinan; M.R. Skokan; T.B. Welch
This paper describes a technology platform being developed for three-dimensional (3-D) integration of thin stacked silicon integrated circuits (ICs). 3-D integration technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator array devices hybridized with silicon read-out electronics. Currently, advanced 3-D integrated infrared focal plane array detectors are being developed within the DARPA vertically integrated sensor arrays (VISA) program. Here, we describe the 3-D integration process flow and demonstrations developed in the VISA program
electronic components and technology conference | 2010
Dean Malta; Christopher Gregory; Dorota Temple; Trevor Knutson; Chen Wang; Thomas Richardson; Yun Zhang; Robert Rhoades
The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology are generally not suitable for TSV fabrication. Therefore, efforts are being made to develop such processes specifically for TSV technology. This paper will describe the development of a void-free Cu electroplating process for TSV filling, along with CMP processing to remove the overburden layer and expose the Cu-filled vias for subsequent metallization. The focus of the paper will be the integration of the TSV plating and CMP processes, with discussion regarding observed integration challenges and their solutions. First, a Cu electroplating process was developed for defect-free, bottom-up filling of silicon vias from 20–200µm in diameter and 150–375µm deep, with aspect ratios from 1:1 to 8:1. Next, CMP tests were conducted using Cu-filled silicon vias of 50µm diameter and 150µm depth, designed for use in a MEMS wafer-level packaging application. These tests indicated that plating nonuniformity and Cu mound defects over filled vias caused significant CMP process issues. The plating process was then modified to eliminate these problems in the Cu films, resulting in improved CMP uniformity and reduced polishing time.
international electron devices meeting | 2006
Dorota Temple; Christopher Bower; Dean Malta; J.E. Robinson; P.R. Coffinan; M.R. Skokan; T.B. Welch
The paper describes a platform technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of sensor and actuator devices hybridized with Si electronics. Among these applications are high performance infrared focal plane array detectors
electronic components and technology conference | 2010
Jason D. Reed; Matthew Lueck; Christopher Gregory; Alan Huffman; John M. Lannon; Dorota Temple
The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10µm and 15µm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99% individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 23 consecutive bond pairs was made with mechanical key, resulting in 92% aggregate channel yield at 10µm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The effects of thermal cycling on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made.
Applied Physics Letters | 2012
Ethan J. D. Klem; Christopher Gregory; Garry Cunningham; Stephen Hall; Dorota Temple; Jay Lewis
Of interest for both photovoltaic and photodetector applications is the ability of colloidal quantum dot (CQD) devices to provide response further into the infrared than is typical for other solution-processable materials. Here, we present a simple heterojunction diode structure that utilizes the extended infrared absorption of PbS CQDs. We show that device performance benefits from a discontinuous exciton blocking layer which improves charge separation without limiting charge extraction. By enhancing charge carrier mobility in the CQD layer, we demonstrate a planar heterostructure device with a power conversion efficiency of 5.2% under 1 sun illumination.