Christopher Gregory

Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects

The fabrication of through-silicon vias (TSVs) is a major component in the development of three-dimensional (3D) integration technology and advanced 3D packaging approaches. The large diameter and length of TSVs, as compared to traditional interconnects, create some unique process challenges. Via plating and chemical-mechanical polishing (CMP) processes used in standard copper interconnect technology are generally not suitable for TSV fabrication. Therefore, efforts are being made to develop such processes specifically for TSV technology. This paper will describe the development of a void-free Cu electroplating process for TSV filling, along with CMP processing to remove the overburden layer and expose the Cu-filled vias for subsequent metallization. The focus of the paper will be the integration of the TSV plating and CMP processes, with discussion regarding observed integration challenges and their solutions. First, a Cu electroplating process was developed for defect-free, bottom-up filling of silicon vias from 20–200µm in diameter and 150–375µm deep, with aspect ratios from 1:1 to 8:1. Next, CMP tests were conducted using Cu-filled silicon vias of 50µm diameter and 150µm depth, designed for use in a MEMS wafer-level packaging application. These tests indicated that plating nonuniformity and Cu mound defects over filled vias caused significant CMP process issues. The plating process was then modified to eliminate these problems in the Cu films, resulting in improved CMP uniformity and reduced polishing time.

High density interconnect at 10µm pitch with mechanically keyed Cu/Sn-Cu and Cu-Cu bonding for 3-D integration

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10µm and 15µm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99% individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 23 consecutive bond pairs was made with mechanical key, resulting in 92% aggregate channel yield at 10µm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The effects of thermal cycling on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made.

Planar PbS quantum dot/C60 heterojunction photovoltaic devices with 5.2% power conversion efficiency

Of interest for both photovoltaic and photodetector applications is the ability of colloidal quantum dot (CQD) devices to provide response further into the infrared than is typical for other solution-processable materials. Here, we present a simple heterojunction diode structure that utilizes the extended infrared absorption of PbS CQDs. We show that device performance benefits from a discontinuous exciton blocking layer which improves charge separation without limiting charge extraction. By enhancing charge carrier mobility in the CQD layer, we demonstrate a planar heterostructure device with a power conversion efficiency of 5.2% under 1 sun illumination.

Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration

The use of collapsible (solder) bump interconnects in pixel detector hybridization has been shown to be very successful. However, as pixel sizes decrease, the use of non-collapsible metal-to-metal bump bonding methods is needed to push the interconnect dimensions smaller. Furthermore, these interconnects are compatible with 3D intgration technologies which are being considered to increase overall pixel and system performance. These metal-to-metal bonding structures provide robust mechanical and electrical connections and allow for a dramatic increase in pixel density. Of particular interest are Cu-Cu thermocompression bonding and Cu/Sn-Cu solid-liquid diffusion bonding processes. Working with Fermilab, RTI undertook a demonstration to show that these bump structures could be reliably used to interconnect devices designed with 20 micron I/O pitch. Cu and Cu/Sn bump fabrication processes were developed to provide a well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. The electrical resistance and yield has been quantified based on electrical measurements of daisy chain test structures and the mechanical strength of the bonding has been quantified through die shear testing. The reliability has been characterized through studies of the impact of thermal exposure on the mechanical performance of the bonds. Cross-section SEM analysis, coupled with high resolution energy dispersive spectroscopy, has provided insight into the physical and chemical nature of the bonding interfaces and aided in the evaluation of the long-term stability of the bonds.

Characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs

Successful implementation of 3D integration technology requires understanding of the unique yield and reliability issues associated with through-silicon vias (TSVs), with adequate design and process considerations to address these issues. This paper relates to the characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs designed for use in 3D Si interposers and 3D wafer-level packaging applications. The paper will describe a variety of methods for characterization of Cu TSV fill quality, microstructure, and thermally-induced TSV height increase known as “copper protrusion” or “copper pumping.” An X-ray imaging method was used for fast, nondestructive analysis of Cu TSV plating profiles and detection of trapped voids. In addition, a plasma focused ion beam (plasma-FIB) process was used to generate high quality cross sections of full TSVs, 50μm in diameter and 150μm depth. Imaging of TSVs by Ga FIB channeling contrast and electron backscattered diffraction (EBSD) provided information about Cu microstructure, including quantitative analysis of grain size. It was observed that TSVs exposed to elevated temperatures exhibited a substantial increase in grain size, which was associated with the Cu protrusion effect. This paper will also report the results of TSV integration with subsequent layers, with analysis of thermo-mechanical failures due to interactions between Cu TSVs and adjacent dielectric layers. The use of an anneal step to stabilize the plated Cu TSVs, prior to build-up of subsequent dielectric layers, will be described.

High Density Metal–Metal Interconnect Bonding for 3-D Integration

3-D integration provides a pathway to achieve high performance microsystems through bonding and interconnection of best-of-breed materials and devices. Bonding of device layers can be accomplished by dielectric bonding and/or metal-metal interconnect bonding with a number of metal-metal systems currently under development. RTI has been investigating Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications. The interconnect pad fabrication processes and the interconnect bonding conditions (pressure and temperature) required for the formation of low resistance (10s of mΩ), high yielding (≥99.98% bond yield), and reliable interconnects are described. The effects of thermal reliability testing (aging) on electrical connectivity and mechanical strength are presented. Results from the two metal-metal interconnect bonding systems are compared in terms of ease of assembly and small pitch (sub-15 μm ) scaling. Methods for obtaining high bond yield at smaller pitches are discussed.

Bonding for 3-D Integration of Heterogeneous Technologies and Materials

Modern electronic applications demand more and more complex, multifunctional microsystems with performance characteristics which can only be achieved by using best-of-breed materials and device technologies. Three-dimensional (3-D) integration of separate, individually complete device layers provides a way to build complex heterogeneous microsystems without compromising the system performance and fabrication yield. In the 3-D integration approach, each device layer is fabricated separately using optimized materials and processes. The layers are bonded and interconnected through area array vertical interconnects with lengths on the order of microns. This paper will review bonding techniques for high density area array 3-D integration of integrated circuits, focusing on techniques suitable for die-to-die and die-to-wafer bonding configurations.

Fabrication of TSV-based silicon interposers

Silicon interposers with through-silicon vias (TSVs) will enable further miniaturization and reduction in power consumption for future electronic systems. The design and method of integration of the TSVs can have a significant effect on the interposer process complexity, yield, and reliability. This paper will compare two different process approaches for Si interposer fabrication. In one approach, TSVs were formed “TSVs last”, following the front-side multi-level metallization (MLM) processing, and were lined with copper, but were not filled. The second approach was a “TSVs first” process in which copper-filled TSVs were formed in silicon wafers prior to frontside MLM processing. These wafers were processed through front-side Cu CMP and back-side wafer thinning, leaving Cu-filled TSVs exposed from both sides. The resulting TSV substrates could then be used for interposer fabrication involving front-side and back-side metal processing. This paper will summarize the fabrication and testing of TSV electrical test structures and interposer wafers using the TSVs-last process. For the TSVs-first process, which is still in development, the paper will review the demonstrations of key process modules and discuss integration and reliability considerations.

Optimization of chemistry and process parameters for void-free copper electroplating of high aspect ratio through-silicon vias for 3D integration

The through-silicon via is a key element in the development of 3D integration technology for new generations of advanced electronic systems. There are several challenges associated with filling these deep, relatively large diameter vias using standard copper electroplating processes, like those common in damascene technology. This paper will summarize a process development for copper electroplating of deep silicon vias in the range of 20–200µm in diameter and 150–375µm in depth. The test vias had aspect ratios ranging from 1.3:1 to 8:1, with sidewalls which were approximately vertical. The paper will discuss copper via plating results with respect to additive component levels, current density, seed layer quality, and sample pretreatments pertaining to wetting of the vias in the plating solution.

High density Cu-Cu interconnect bonding for 3-D integration

The demand for more complex and multifunctional microsystems with enhanced performance characteristics is driving the electronics industry toward the use of best-of-breed materials and device technologies. Three-dimensional (3-D) integration enables building such high performance microsystems through bonding and interconnection of individually optimized device layers. Bonding of device layers can be achieved through polymer bonding or metal-metal interconnect bonding with a number of metal-metal systems (e.g. Cu-Cu, Cu/Sn-Cu, etc.) currently under development. RTI has been investigating and characterizing Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications, demonstrating bonding between pads less than 15 microns in diameter for large area array configurations. Cu and Cu/Sn bump fabrication processes were developed that provide well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. In this paper, the effects of Cu interconnect bonding parameters (pressure and temperature) and thermal reliability testing (thermal cycling and aging) on electrical connectivity and mechanical strength are presented and compared to Cu/Sn-Cu interconnect bonding with an eye toward small pitch scaling and ease of assembly. The conditions for producing Cu-Cu bond strengths ≫ 110 MPa and electrical connectivity as high as 99.999% are described.