Matthew Lueck

High density interconnect at 10µm pitch with mechanically keyed Cu/Sn-Cu and Cu-Cu bonding for 3-D integration

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10µm and 15µm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99% individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 23 consecutive bond pairs was made with mechanical key, resulting in 92% aggregate channel yield at 10µm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The effects of thermal cycling on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made.

Effects of Assembly Process Parameters on the Structure and Thermal Stability of Sn-Capped Cu Bump Bonds

Non-collapsible Cu-Sn bumps (Cu pillars capped with a thin layer of Sn) have been studied recently as a means to vertically interconnect device layers, achieving 3D integrated circuits. The use of Cu-Sn bump structures is attractive for 3D integration for two primary reasons: 1) the rigid nature of the Cu bump allows for very fine pitch interconnections to be made with less risk of bridging than would exist with collapsible solder bumps, and 2) the joint created when bonding Cu and Cu-Sn bumps remelts at a higher temperature than the formation temperature, which allows for the stacking of multiple layers of devices without disturbing the interconnections achieved in previous bonding events. In order to understand the optimal structure and bonding process for fine pitch Cu-Sn bumps, a study was done to investigate the effects of Sn thickness and bonding pressure on the thickness and chemical composition of the bondline between Cu and Cu-Sn bumps. The thermal stability of the bondline was studied by subjecting bonded test samples to multiple temperature/pressure cycles. The bonding strength was evaluated through die shear tests, and the results were correlated with the parameters of the bump structure and with process parameters.

Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration

The use of collapsible (solder) bump interconnects in pixel detector hybridization has been shown to be very successful. However, as pixel sizes decrease, the use of non-collapsible metal-to-metal bump bonding methods is needed to push the interconnect dimensions smaller. Furthermore, these interconnects are compatible with 3D intgration technologies which are being considered to increase overall pixel and system performance. These metal-to-metal bonding structures provide robust mechanical and electrical connections and allow for a dramatic increase in pixel density. Of particular interest are Cu-Cu thermocompression bonding and Cu/Sn-Cu solid-liquid diffusion bonding processes. Working with Fermilab, RTI undertook a demonstration to show that these bump structures could be reliably used to interconnect devices designed with 20 micron I/O pitch. Cu and Cu/Sn bump fabrication processes were developed to provide a well-controlled surface topography necessary for the formation of low resistance, high yielding, and reliable interconnects. The electrical resistance and yield has been quantified based on electrical measurements of daisy chain test structures and the mechanical strength of the bonding has been quantified through die shear testing. The reliability has been characterized through studies of the impact of thermal exposure on the mechanical performance of the bonds. Cross-section SEM analysis, coupled with high resolution energy dispersive spectroscopy, has provided insight into the physical and chemical nature of the bonding interfaces and aided in the evaluation of the long-term stability of the bonds.

Characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs

Successful implementation of 3D integration technology requires understanding of the unique yield and reliability issues associated with through-silicon vias (TSVs), with adequate design and process considerations to address these issues. This paper relates to the characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs designed for use in 3D Si interposers and 3D wafer-level packaging applications. The paper will describe a variety of methods for characterization of Cu TSV fill quality, microstructure, and thermally-induced TSV height increase known as “copper protrusion” or “copper pumping.” An X-ray imaging method was used for fast, nondestructive analysis of Cu TSV plating profiles and detection of trapped voids. In addition, a plasma focused ion beam (plasma-FIB) process was used to generate high quality cross sections of full TSVs, 50μm in diameter and 150μm depth. Imaging of TSVs by Ga FIB channeling contrast and electron backscattered diffraction (EBSD) provided information about Cu microstructure, including quantitative analysis of grain size. It was observed that TSVs exposed to elevated temperatures exhibited a substantial increase in grain size, which was associated with the Cu protrusion effect. This paper will also report the results of TSV integration with subsequent layers, with analysis of thermo-mechanical failures due to interactions between Cu TSVs and adjacent dielectric layers. The use of an anneal step to stabilize the plated Cu TSVs, prior to build-up of subsequent dielectric layers, will be described.

High Density Metal–Metal Interconnect Bonding for 3-D Integration

3-D integration provides a pathway to achieve high performance microsystems through bonding and interconnection of best-of-breed materials and devices. Bonding of device layers can be accomplished by dielectric bonding and/or metal-metal interconnect bonding with a number of metal-metal systems currently under development. RTI has been investigating Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications. The interconnect pad fabrication processes and the interconnect bonding conditions (pressure and temperature) required for the formation of low resistance (10s of mΩ), high yielding (≥99.98% bond yield), and reliable interconnects are described. The effects of thermal reliability testing (aging) on electrical connectivity and mechanical strength are presented. Results from the two metal-metal interconnect bonding systems are compared in terms of ease of assembly and small pitch (sub-15 μm ) scaling. Methods for obtaining high bond yield at smaller pitches are discussed.

Applying microfabrication to helical vacuum electron devices for THz applications

A new class of helical THz vacuum electron devices is under development using unconventional applications of microfabrication technology, modern computer modeling, and novel materials. The resulting slow wave circuits consist of a coil of gold wire, smaller in outside diameter than a human hair, supported by a thin diamond sheet and suspended within a diamond box. This configuration will extend the operating range of the helical slow wave circuit into the THz frequency band. Previously, the advantages of the wide bandwidth and high efficiency of the helical slow wave circuit have been available only for operation at frequencies below 50 or 60 GHz because of the difficulty of winding small coils of wire and because it is impossible to transmit a significant beam current through the small aperture offered by the center of the helix. These obstacles are overcome by fabricating the helices lithographically and by passing the electron beam around the outside of the helix. The design and fabrication of a 650 GHz backward wave oscillator (BWO) will be described as well as proposed applications of this technology to traveling wave tubes (TWTs) operating at frequencies as high as 1.0 THz. A THz amplifier, possibly with multioctave bandwidth, would have a wide range of important applications.

Bonding for 3-D Integration of Heterogeneous Technologies and Materials

Modern electronic applications demand more and more complex, multifunctional microsystems with performance characteristics which can only be achieved by using best-of-breed materials and device technologies. Three-dimensional (3-D) integration of separate, individually complete device layers provides a way to build complex heterogeneous microsystems without compromising the system performance and fabrication yield. In the 3-D integration approach, each device layer is fabricated separately using optimized materials and processes. The layers are bonded and interconnected through area array vertical interconnects with lengths on the order of microns. This paper will review bonding techniques for high density area array 3-D integration of integrated circuits, focusing on techniques suitable for die-to-die and die-to-wafer bonding configurations.

95 GHz helical TWT design

The helical slow-wave circuit is an attractive choice for traveling wave tube amplifiers (TWTAs) because of its inherently large bandwidth and relatively high RF efficiency. Unfortunately, as the operational frequency increases beyond Q-or V-band, its use has been limited by conventional fabrication techniques, and by the difficulty of passing enough current through the center of such a small structure. This paper describes the design and fabrication status of a 95 GHz TWT using microfabrication technology to create and assemble the helix. The electron beam propagates as two kidney shaped beamlets between the helix outer diameter and barrel.

Microfabrication of diamond-based slow-wave circuits for mm-wave and THz vacuum electronic sources

Planar and helical slow-wave circuits for THz radiation sources have been made using novel microfabrication and assembly methods. A biplanar slow-wave circuit for a 650 GHz backward wave oscillator (BWO) was fabricated through the growth of diamond into high aspect ratio silicon molds and the selective metallization of the tops and sidewalls of 90 μm tall diamond features using lithographically created shadow masks. Helical slow-wave circuits for a 650 GHz BWO and a 95 GHz traveling wave tube were created through the patterning of trenches in thin film diamond, electroplating of gold half-helices, and high accuracy bonding of helix halves. The development of new techniques for the microfabrication of vacuum electronic components will help to facilitate compact and high-power sources for terahertz range radiation.

Fabrication of TSV-based silicon interposers

Silicon interposers with through-silicon vias (TSVs) will enable further miniaturization and reduction in power consumption for future electronic systems. The design and method of integration of the TSVs can have a significant effect on the interposer process complexity, yield, and reliability. This paper will compare two different process approaches for Si interposer fabrication. In one approach, TSVs were formed “TSVs last”, following the front-side multi-level metallization (MLM) processing, and were lined with copper, but were not filled. The second approach was a “TSVs first” process in which copper-filled TSVs were formed in silicon wafers prior to frontside MLM processing. These wafers were processed through front-side Cu CMP and back-side wafer thinning, leaving Cu-filled TSVs exposed from both sides. The resulting TSV substrates could then be used for interposer fabrication involving front-side and back-side metal processing. This paper will summarize the fabrication and testing of TSV electrical test structures and interposer wafers using the TSVs-last process. For the TSVs-first process, which is still in development, the paper will review the demonstrations of key process modules and discuss integration and reliability considerations.