Zhibin Xiong

Characteristics of high-K spacer offset-gated polysilicon TFTs

In this paper, a self-aligned offset-gated poly-Si TFT using high-K dielectric (Hafnium oxide, HfO/sub 2/) spacers for channel scaled-down system-on-panel applications is experimentally demonstrated for the first time. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. Numerical simulations show that with the high vertical field induced underneath the high-K spacer, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, comparing to the conventional lightly doped drain or oxide spacer TFTs. The experimental on-state current in the HfO/sub 2/ spacer offset-gated poly-Si TFT is approximately two times higher than that of the conventional oxide spacer TFT with the same leakage current.

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.

A novel self-aligned offset-gated polysilicon TFT using high-/spl kappa/ dielectric spacers

In this letter, a novel self-aligned offset-gated Poly-Si thin-film transistor (TFT) using high-/spl kappa/ dielectric Hafnium oxide (HfO/sub 2/) spacers is proposed and demonstrated. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. The permittivity of the deposited HfO/sub 2/ is approximately 20. Experimental results show that with the high vertical field induced underneath the high-/spl kappa/ spacers, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, compared to the conventional lightly doped drain or oxide spacer TFTs. The on-state current in the offset-gated Poly-Si TFT using the HfO/sub 2/ spacers is approximately two times higher than that of the conventional oxide spacer TFT.

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.

A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.

Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy

In this paper, a simple high performance double-gate metal oxide semiconductor field effect transistor (MOSFET) using lateral solid-phase epitaxy (LSPE) is experimentally demonstrated and characterized. The thin channel of the double-gate MOSFET was obtained using the high quality LSPE crystallized layer. The fabricated double-gate MOSFET provides good current drive capability and steep subthreshold slope, and they are approximately 350 /spl mu/A//spl mu/m (@ V/sub ds/ = 2.5 V and V/sub gs/ - V/sub T/ = 2.5 V) and 78 mV/dec for the devices with 0.5 /spl mu/m channel length. Compared to the conventional single-gate transistor, the double-gate NMOSFET fabricated on the LSPE layer has better V/sub T/ roll-off characteristics, DIBL effect, and 1.72 times higher current drive. The peak effective electron mobility of the LSPE crystallized layer is approximately 382 cm/sup -2//V.s.

A novel ultrathin vertical channel NMOSFET with asymmetric fully overlapped LDD

In this letter, a novel ultrathin vertical channel (UTVC) NMOSFET with asymmetric fully overlapped lightly doped drain (LDD) is proposed and demonstrated using solid-phase epitaxy (SPE). A boron-doped polycrystalline Si/sub 0.5/Ge/sub 0.5/ gate was used to tune the threshold voltage, a lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel was used to suppress the electron mobility degradation, and an asymmetric fully overlapped LDD was adopted to reduce the series resistance as compared to the conventional LDD. Devices with 50-nm channel length were achieved by using 15-nm ultrathin channel thickness, and they provided high current drive, steep subthreshold slope, and good V/sub T/ roll-off characteristics.

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.

A New Isolation Technology for Automotive Power-Integrated-Circuit Applications

In this paper, a new bulk silicon isolation structure with wafer-thick trenches is proposed for automotive (42 V) power-integrated-circuit applications. This technology provides the advantages of complete isolation with lower wafer cost and higher thermal-dissipation capability as compared with the silicon-on-insulator technology. Experimental results show that the new isolation structure can provide complete electrical isolation and with a 13% reduction in thermal resistance.

A novel drift region self-aligned SOI power MOSFET using a partial exposure technique

In this paper, a novel drift region self-aligned SOI power MOSFET using a partial exposure technique is proposed and demonstrated. The drift region is self-aligned to the channel and was achieved using a simple process without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs with a length ranging from 0.3/spl mu/m to a few microns. The fabricated SOI power device has a breakdown voltage of over 20V. Using a 0.7/spl mu/m non-silicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 GHz and 13.7GHz, respectively.