Jon J. Candelaria

Profile study of a graded epitaxial stack and its impact on high performance bipolar devices

Advanced MOSAIC V technology uses a graded epitaxial stack of 0-9μm n epitaxial layer grown on an n + buried layer which has been implanted into an inirinsic epitaxial layer. A study of the intrinsic epitaxial layer profile is critical for reducing the collector substrate (Ccs) capacitance which adversely affects the ECL gate delay. The importance of the intrinsic epitaxial layer profile for the performance of trench isolated high performance ASIC bipolar transistors is considered.