Peter J. Zdebel

Measurement of collector and emitter resistances in bipolar transistors

New DC methods to measure the collector resistance R/sub C/ and emitter resistance R/sub E/ are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R/sub C/. R/sub E/ is obtained from the measured lateral portion of R/sub C/ and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R/sub C/ on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R/sub C/ is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R/sub E/ a value for the specific contact resistance for the polysilicon emitter contact of rho /sub c/ equivalent to 50 Omega - mu m/sup 2/ is obtained. >

Novel isolation process using selective polysilicon filled trench technology for high speed bipolar circuits

Zero encroachment variable-width trench isolation (ZERO) with selective polycrystalline refill has been developed for emitter coupled logic (ECL) circuits. Subsequent oxidation of the selective polysilicon film produces a box-type oxide isolation with vertical sidewalls, no faceting, and zero encroachment. From the planarization point of view, selective polysilicon growth reduces the process complexity of LPCVD (low-pressure chemical vapor deposition) polysilicon-filled single-width trench technology. The selective polysilicon growth also facilitates variable-width trench isolation. Furthermore, it eliminates the faceting problem associated with selective monosilicon trench refill. Bipolar devices were built with variable-width trenches of 1 mu m depth. Gate delay performance was improved by 40-45% as compared to recessed LOCOS isolated circuits.<<ETX>>

Low power/low voltage CMOS technologies, a comparative analysis

Abstract Advanced CMOS device and process technologies will be discussed with respect to low power and low voltage performance characteristics based on various device scaling and structure principles. A synopsis of recently published technologies is presented with the purpose of identifying key approaches and analyzing common and diverse features and merits.

Low Power/Low Voltage silicon and GaAs technologies in portable communication products: Profound changes in technology migration

Abstract Low Voltage/Low Power silicon and GaAs device and process technologies will be discussed with respect to critical benchmark parameters. Special consideration is given to technology aspects as they refer to applications in portable communication products. Portable products are of particular interest since the subsystems cover a diversified range of technology requirements with respect to RF, digital, and analog signal processing under the most stringent power constraints.

Device simulations for low voltage/low power silicon CMOS device design

Abstract Device simulations are becoming an increasingly attractive alternative to traditional, experiment-based technology development. This is due to the sky-rocketing development costs, increasing process complexity and finally the increasing maturity of the device simulation tools. In this chapter, we discuss some of the issues involved in low power CMOS device design using full-fledged (two-dimensional) numerical device simulations. The roles played by vertical channel profile engineering, the halo/pocket implants and shallow source / drain extensions in minimizing short channel effects is discussed.