Jonathan Joseph Coleman

Micro-fabricated stylus ion trap

An electroformed, three-dimensional stylus Paul trap was designed to confine a single atomic ion for use as a sensor to probe the electric-field noise of proximate surfaces. The trap was microfabricated with the UV-LIGA technique to reduce the distance of the ion from the surface of interest. We detail the fabrication process used to produce a 150 μm tall stylus trap with feature sizes of 40 μm. We confined single, laser-cooled, (25)Mg(+) ions with lifetimes greater than 2 h above the stylus trap in an ultra-high-vacuum environment. After cooling a motional mode of the ion at 4 MHz close to its ground state ( = 0.34 ± 0.07), the heating rate of the trap was measured with Raman sideband spectroscopy to be 387 ± 15 quanta/s at an ion height of 62 μm above the stylus electrodes.

Multilayer metal micromachining for THz waveguide fabrication

Thick multi-layer metal stacking offers the potential for fabrication of rectangular waveguide components, including horn antennas, couplers, and bends, for operation at terahertz frequencies, which are too small to machine traditionally. Air-filled, TE10, rectangular waveguides for 3 THz operation were fabricated using two stacked electroplated gold layers on both planar and non-planar substrates. The initial layer of lithography and electroplating defined 37 micrometer tall waveguide walls in both straight and meandering geometries. The second layer, processed on top of the first, defined 33 micrometer thick waveguide lids. Release holes periodically spaced along the center of the lids improved resist clearing from inside of the electroformed rectangular channels. Processing tests of hollow structures on optically clear, lithium disilicate substrates allowed confirmation of resist removal by backside inspection.

Optimizing galvanic pulse plating parameters to improve indium bump to bump bonding

The plating characteristics of a commercially available indium plating solution are examined and optimized to help meet the increasing performance demands of integrated circuits requiring substantial numbers of electrical interconnections over large areas. Current fabrication techniques rely on evaporation of soft metals, such as indium, into lift-off resist profiles. This becomes increasingly difficult to accomplish as pitches decrease and aspect ratios increase. To minimize pixel dimensions and maximize the number of pixels per unit area, lithography and electrochemical deposition (ECD) of indium has been investigated. Pulse ECD offers the capability of improving large area uniformity ideal for large area device hybridization. Electrochemical experimentation into lithographically patterned molds allow for large areas of bumps to be fabricated for low temperature indium to indium bonds. The galvanic pulse profile, in conjunction with the bath configuration, determines the uniformity of the plated array. This pulse is manipulated to produce optimal properties for hybridizing arrays of aligned and bonded indium bumps. The physical properties of the indium bump arrays are examined using a white light interferometer, a SEM and tensile pull testing. This paper provides details from the electroplating processes as well as conclusions leading to optimized plating conditions.