Jonathan Leu

Single-chip microprocessor that communicates directly using light

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic–photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Open foundry platform for high-performance electronic-photonic integration

This paper presents photonic devices with 3 dB/cm waveguide loss fabricated in an existing commercial electronic 45 nm SOI-CMOS foundry process. By utilizing existing front-end fabrication processes the photonic devices are monolithically integrated with electronics in the same physical device layer as transistors achieving 4 ps logic stage delay, without degradation in transistor performance. We demonstrate an 8-channel optical microring-resonator filter bank and optical modulators, both controlled by integrated digital circuits. By developing a device design methodology that requires zero process infrastructure changes, a widely available platform for high-performance photonic-electronic integrated circuits is enabled.

Addressing link-level design tradeoffs for integrated photonic interconnects

Integrated photonic interconnects have emerged recently as a potential solution for relieving on-chip and chip-to-chip bandwidth bottlenecks for next-generation many-core processors. To help bridge the gap between device and circuit/system designers, and aid in understanding of inherent photonic link tradeoffs, we present a set of link component models for performing interconnect design-space exploration connected to the underlying device and circuit technology. To compensate for process and thermal-induced ring resonator mismatches, we take advantage of device and circuit characteristics to propose an efficient ring tuning solution. Finally, we perform optimization of a wavelength-division-multiplexed link, demonstrating the link-level interactions between components in achieving the optimal degree of parallelism and energy-efficiency.

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes, however, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few process changes as possible. In this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in process-native polysilicon, we introduce deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the fully polysilicon-based photonics platform. Transceiver circuits take advantage of photonic device integration, achieving 350 fJ/b transmit and 71 µA pp BER = 10 -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with 9-wavelength 45 Gb/s transmit/receive data-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A 5 m optical chip-to-chip link achieves 5 Gb/s while consuming 3 pJ/b and 12 pJ/bit of circuit and optical energy, respectively.

A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI

Integrated photonic interconnect technology presents a disruptive alternative to electrical I/O for many VLSI applications. Superior bandwidth-density and energy-efficient operation can be realized through dense wavelength-division multiplexing (DWDM) and lower transmission losses. There are two main paths towards an integrated platform. Hybrid/heterogeneous designs [1-3] enable each component to be custom-tailored, but suffer from large packaging parasitics, increased manufacturing costs due to requisite process flows, and costly 3D integration or microbump packaging. Monolithic integration mitigates integration overheads, but has not penetrated deeply-scaled technologies due to necessary process customizations [4]. The first monolithic integration of photonic devices and electronic-photonic operation in sub-100 nm (45 nm SOI process with zero foundry changes) is demonstrated in [5]. This paper presents a monolithically integrated optical modulator with a new all-digital driver circuit in a commercial 45nm SOI process. The waveform-conditioning driver circuit enables the carrier-injection modulator to operate at 2.5Gb/s with an energy-cost of 1.23pJ/b, making it ~4× faster and more energy-efficient than the previous monolithically integrated driver/modulator presented in [5].

Injection-locked clock receiver for monolithic optical link in 45nm SOI

This paper presents a compact, low-power injection-locked clock receiver for large-scale integrated optical interconnects. The injection-locked design provides high input sensitivity when compared to the TIA-less integrating clock receiver design. It also breaks the gain/bandwidth tradeoff of a traditional transimpedance amplifier (TIA) receiver, with a self-adjusting mechanism to increase robustness. The receiver is designed in 45nm SOI and shown to operate from 1.0 GHz to 3.0 GHz while consuming from 186μW to 444 μW, with an input sensitivity from 8.6μA to 33.2μA and output jitter σ within 1 %UI.

Analog Logic Automata

Analog logic circuits work on digital problems using an analog representation of the digital variables, relaxing the state space of the digital system from the vertices of a hypercube to the interior. This lets us gain speed, power, and accuracy over digital implementations. Logic automata are distributed, scalable and programmable digital computation media with local connections and logic operations. Here we propose analog logic automata (ALA), which relax binary constraints on logic automata states and introduce programmability into analog logic circuits. The localized interaction and scalability of the ALA provide a new way to do neuromorphic engineering, enabling systematic designs in a digital work flow. Low-power, biomedical, decoding and communication applications are described and a 3times3 ALA chip is prototyped, which works at 50 kHz, with a power consumption of 64 muW. With the chip configured as a programmable noise-locked loop (NLL), we obtain a bit error rate (BER) of 1E-7 at an SNR of -1.13 dB.

Electro-optical co-simulation for integrated CMOS photonic circuits with VerilogA

We present a Cadence toolkit library written in VerilogA for simulation of electro-optical systems. We have identified and described a set of fundamental photonic components at the physical level such that characteristics of composite devices (e.g. ring modulators) are created organically - by simple instantiation of fundamental primitives. Both the amplitude and phase of optical signals as well as optical-electrical interactions are simulated. We show that the results match other simulations and analytic solutions that have previously been compared to theory for both simple devices, such as ring resonators, and more complicated devices and systems such as single-sideband modulators, WDM links and Pound Drever Hall Locking loops. We also illustrate the capability of such toolkit for co-simulation with electronic circuits, which is a key enabler of the electro-optic system development and verification.

Low loss waveguide integration within a thin-SOI CMOS foundry

By requiring zero process changes and by complying with established electronic circuit design rules, photonic devices formed with 3dB/cm waveguides were fabricated alongside transistors achieving 4ps stage delay in a 45nm thin-SOI CMOS foundry.