Jonathan T. Shaw

Integration of Self-Assembled Redox Molecules in Flash Memory Devices

Self-assembled monolayers (SAMs) of either ferrocenecarboxylic acid or 5-(4-Carboxyphenyl)-10,15,20-triphenyl-porphyrin-Co(II) (CoP) with a high- dielectric were integrated into the Flash memory gate stack. The molecular reduction-oxidation (redox) states are used as charge storage nodes to reduce charging energy and memory window variations. Through the program/erase operations over tunneling barriers, the device structure also provides a unique capability to measure the redox energy without strong orbital hybridization of metal electrodes in direct contact. Asymmetric charge injection behavior was observed, which can be attributed to the Fermi-level pinning between the molecules and the high- dielectric. With increasing redox molecule density in the SAM, the memory window exhibits a saturation trend. Three programmable molecular orbital states, i.e., CoP0, CoP1-, and CoP2-, can be experimentally observed through a charge-based nonvolatile memory structure at room temperature. The electrostatics is determined by the alignment between the highest occupied or the lowest unoccupied molecular orbital (HOMO or LUMO, respectively) energy levels and the charge neutrality level of the surrounding dielectric. Engineering the HOMO-LUMO gap with different redox molecules can potentially realize a multibit memory cell with less variation.

A Ferroelectric and Charge Hybrid Nonvolatile Memory—Part II: Experimental Validation and Analysis

Part I of this article introduced the concept and operation of the novel hybrid memory, integrating ferroelectric polarization and nonvolatile charge injection. In Part II, we demonstrate the experimental validation of this hybrid design. One-transistor memory cells were fabricated with polyvinylidene fluoride-trifluoroethylene [P(VDF-TrFE)] as the ferroelectric and HfO2 as the charge trap layer. Hybrid devices showed larger memory window and longer retention time compared to conventional FE-FETs with the same effective oxide thickness. Pulsed measurements were performed on metal-ferroelectric-metal capacitors to estimate switching delay in the P(VDF-TrFE) thin film. Field enhancement in the tunnel oxide resulted in pronounced electron injection from the gate compared with gate injection Flash memory cells. Hybrid devices also exhibited higher program efficiencies against the FE-FET due to the contribution from these injected electrons. The presence of the tunnel oxide in hybrid devices showed over 20× reduction in gate leakage, which resulted in 100 × improvement in cycling endurance against FE-FETs.

A Ferroelectric and Charge Hybrid Nonvolatile Memory—Part I: Device Concept and Modeling

We present a new one-transistor hybrid nonvolatile memory based on the combination of two distinctive mechanisms, namely, remanent polarization in ferroelectrics and charge injection into floating nodes. The gate stack design and the memory operation of the hybrid device are aimed to offer mutually complementing benefits between the two mechanisms, thereby presenting superior performance over conventional ferroelectric (FE) FET and gate injection-based Flash memory. During program operation, a high negative bias at the gate orients the ferroelectric polarization to the applied field. In addition, electrons at the gate electrode also tunnel into the floating nodes located between the ferroelectric thin film and the thin top tunnel dielectric and increase the total memory window. High electric displacement in the ferroelectric enables field enhancement in the tunnel dielectric for faster program and erase operations. During retention, the injected electrons reduce the depolarization field in the ferroelectrics, and the remanent polarization reduces the electric field in the tunnel oxide, which helps in the longer retention of the programmed state by the two additive memory mechanisms. Part I evaluates the benefits of the hybrid gate stack through 1-D simulations incorporating the polarization-field (P-E) hysteresis in the ferroelectric layer. The simulations provide a guideline for optimal gate stack design of the proposed hybrid memory. The following Part II then discusses the fabrication and experimental validation.

Statistical Metrology of Metal Nanocrystal Memories With 3-D Finite-Element Analysis

We study the parametrical yield of memory windows for the metal nanocrystal (NC) Flash memories with consideration of the 3-D electrostatics and channel percolation effects. Monte Carlo parametrical variation that accounts for the number and size fluctuations in NCs as well as channel length is used to determine the threshold voltage distribution and bit error rate for gate length scaling to 20 nm. Devices with nanowire-based channels are compared with planar devices having the same gate stack structure. Scalability prediction by 1-D analysis is found to be very different from 3-D modeling due to underestimation of effective NC coverage and failure to consider the 3-D nature of the channel percolation effect.

Flash Memory Scaling: From Material Selection to Performance Improvement

Below the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

A hybrid ferroelectric and charge nonvolatile memory

We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.

Interface and oxide quality of CoFeB/MgO/Si tunnel junctions

Magnetic tunnel junction (MTJ) has attracted great interest due to its high tunneling magnetoresistance (TMR) ratio,1 where sputter deposition of MgO between CoFeB electrodes is a strong candidate. The improvement in TMR is believed to result from B diffusion into the MgO to form a polycrystalline Mg-B-O layer with a shaper interface after annealing.2 Decrease in trap states can lead to smaller leakage currents and improvement in tunneling conductance. Therefore, a thorough electrical characterization on the CoFeB/Mg-B-O quality is crucial to model the TMR increase and associated reliability. Although the trap charge in the MTJ structure will change the tunneling path and cause serious parametric drift, it is difficult to directly measure its magnitude. Instead, we made CoFeB/MgO/Si MOS capacitors with process flow illustrated in Fig. 1, which can independently determine the interface traps, oxide charge and stress-induced leakage current (SILC) through conductance, high-frequency capacitance-voltage (HFCV) and IV measurements. We can then characterize the boron diffusion and annealing effects on Mg-B-O.

Ultra-thin-body PECVD Ge TFT low-voltage flash memory cell with high-k dielectrics for three-dimensional integration

As the scaling of conventional bulk Si flash memory cells approaches its fundamental limits, innovative 3D stacking and new materials must be considered. Ge is one of the promising candidates due to its attractive properties including higher mobility [1], smaller bandgap for supply voltage scaling, and lower processing temperature for compatibility with high-k dielectric [2] and 3D stack technology. Hence, a study the Ge UTB (ultra thin body) structure is pertinent for understanding its prospect as a viable solution [3]. Unlike silicon, however, the lack of a sufficiently stable native oxide hinders the passivation of Ge surfaces. The native germanium oxide is hygroscopic and water-soluble. Several gate dielectric materials with thick EOT on Ge have been reported [4] in early 1990s. Al2O3 has emerged as one of the most promising high-k gate dielectrics for Ge MOSFET and TFT [5] to cope with the issue of the native Ge oxide [6]. In this study, we demonstrate the material and electrical characteristics of stackable Ge TFT flash memory cell with Al2O3 high-k tunnel dielectric, metal NCs and (Ti,Dy)xOy control dielectric. Our proposed planar thin-film process is a simple batch process, and can therefore be used with relatively small cost increase.

3D Finite-Element Analysis of Metal Nanocrystal Memories Variations

We have shown the process variation effects from nanocrystal size, density, registry and gate length in 20-90 nm metal nanocrystal memory technology by 3D finite-element analysis. Conventional ID analysis in the gate stack will result in severe miscalculation of bit-error-rate due to neglecting the fringing fields and percolation path in the memory cell. We also present the statistical metrology on memory windows from nanocrystal placement control and the use of nanowire devices. We conclude that the self-assembled nanocrystals in the gate stack can fit the parametric yield required for 20 nm technology.

“Nothing” can be better: Study of porosity in the charge trap layer of Flash memory

Discrete charge storage devices based on traps and nanocrystals (NCs) are shown to alleviate the problems of stress induced leakage currents (SILC) that ultimately limits the tunnel oxide scaling. Also, electric field enhancement in the tunnel oxide due to metal NCs1 boosts carrier injection efficiency from the channel thereby lowering program/erase voltages. This study investigates another possibility of generating such field asymmetry in the gate stack through the use of nano-porous dielectrics. The inherent difference in programming and retention mechanisms (F-N against direct tunneling) may be further widened through engineered pores. We investigate the effect of nano pores (NPs) in the charge storage layer through simulation and then present experimental results of porous TiO2.