Kshitij Auluck

A Ferroelectric and Charge Hybrid Nonvolatile Memory—Part II: Experimental Validation and Analysis

Part I of this article introduced the concept and operation of the novel hybrid memory, integrating ferroelectric polarization and nonvolatile charge injection. In Part II, we demonstrate the experimental validation of this hybrid design. One-transistor memory cells were fabricated with polyvinylidene fluoride-trifluoroethylene [P(VDF-TrFE)] as the ferroelectric and HfO2 as the charge trap layer. Hybrid devices showed larger memory window and longer retention time compared to conventional FE-FETs with the same effective oxide thickness. Pulsed measurements were performed on metal-ferroelectric-metal capacitors to estimate switching delay in the P(VDF-TrFE) thin film. Field enhancement in the tunnel oxide resulted in pronounced electron injection from the gate compared with gate injection Flash memory cells. Hybrid devices also exhibited higher program efficiencies against the FE-FET due to the contribution from these injected electrons. The presence of the tunnel oxide in hybrid devices showed over 20× reduction in gate leakage, which resulted in 100 × improvement in cycling endurance against FE-FETs.

A Ferroelectric and Charge Hybrid Nonvolatile Memory—Part I: Device Concept and Modeling

We present a new one-transistor hybrid nonvolatile memory based on the combination of two distinctive mechanisms, namely, remanent polarization in ferroelectrics and charge injection into floating nodes. The gate stack design and the memory operation of the hybrid device are aimed to offer mutually complementing benefits between the two mechanisms, thereby presenting superior performance over conventional ferroelectric (FE) FET and gate injection-based Flash memory. During program operation, a high negative bias at the gate orients the ferroelectric polarization to the applied field. In addition, electrons at the gate electrode also tunnel into the floating nodes located between the ferroelectric thin film and the thin top tunnel dielectric and increase the total memory window. High electric displacement in the ferroelectric enables field enhancement in the tunnel dielectric for faster program and erase operations. During retention, the injected electrons reduce the depolarization field in the ferroelectrics, and the remanent polarization reduces the electric field in the tunnel oxide, which helps in the longer retention of the programmed state by the two additive memory mechanisms. Part I evaluates the benefits of the hybrid gate stack through 1-D simulations incorporating the polarization-field (P-E) hysteresis in the ferroelectric layer. The simulations provide a guideline for optimal gate stack design of the proposed hybrid memory. The following Part II then discusses the fabrication and experimental validation.

Ferroelectric-Assisted Dual-Switching Speed DRAM–Flash Hybrid Memory

This paper presents a novel one-transistor low-voltage DRAM-Flash hybrid memory. The proposed device integrates ferroelectric thin film and nonvolatile charge injection, and demonstrates two modes of operations: 1) a fast (10-100 ns) DRAM mode with ~ 103 s of retention, associated with ferroelectric switching, and 2) a slower (0.1-1 ms) Flash mode with long retention time, from charge tunneling into the floating nodes. The time evolution of the electric field in the ferroelectric and the tunnel oxide is shown to naturally establish the two-step mechanism during the program operation. The complementary characteristics of ferroelectric switching and gate-charge injection enable low-voltage program/erase (±8 V), reasonable memory window (0.8 V), and long retention time. Devices were fabricated with the lead zirconatetitanate thin film as the ferroelectric layer and Au nanocrystals for gate-injected electron storage. Pulsed programming measurements were also performed to distinguish the memory window obtained from the two mechanisms in DRAM and Flash operations.

Circuit Models for Ferroelectrics—Part I: Physics of Polarization Switching

We present a physical circuit model of ferroelectric (FE) polarization switching for the analysis and design of hybrid FE-CMOS circuits. Stochastic geometry is applied to domain nucleation, growth, and coalescence under arbitrary voltage and current input signals. The circuit model is first constructed for ideal FE capacitors and then extended to the realistic effects of lateral scaling, anisotropic growth, and disorder in polycrystalline films. Reliability degradation by imprint and fatigue is also incorporated. The interaction of model parameters and circuit design for three different nonvolatile latch topologies is presented in Part II.

Circuit Models for Ferroelectrics—Part II: Analysis of FE-Nonvolatile Latches

We present a detailed analysis of hybrid ferroelectric (FE)-CMOS nonvolatile latches, based on simulations with the unified physical circuit model from Part-I and experimental verification with circuit measurements. Hybrid FE-CMOS latches are categorized into three classes by the circuit topology of the readout operation. The effect of the physical model parameters is studied in all regions of operation by a variational analysis. Design intuition for the signal timing and sensing margin is provided and the strategies for the design optimization are discussed. Signal degradation due to imprint and fatigue in each latch topology is also compared.

Dynamic Modeling of Dual Speed Ferroelectric and Charge Hybrid Memory

This paper presents a physical model for program and retention transients in ferroelectric (FE) and charge hybrid nonvolatile memory. A region-by-region statistical model for domain switching in polycrystalline FEs was incorporated with the tunneling current simulations to predict the memory window (AVTH) evolution during program and retention operations. The simulations validated the two-step program mechanism experimentally observed in such memories: rapid initial domain switching on account of high fields in the FE layer followed by field enhancement in the tunneling dielectric which initiates electron injection into the storage nodes. Further, these simulations were shown to accurately account for individual ΔVTH from the two additive memory mechanisms at all program times. The depolarization effect was shown to be dominant for ΔVTH loss at short and moderate retention time scales (<;100 s). This model was further used to provide realistic estimates in achieving dual speed program and the corresponding dual mode retention characteristics akin to a DRAM and flash hybrid operation.

Switching dynamics in ferroelectric-charge hybrid nonvolatile memory

A statistical model is proposed for ferroelectric (FE) polarization switching response during program and retention in FE-charge hybrid nonvolatile memory. During the program pulse, high fields first occur in the FE layer and then transfer to tunnel oxide after FE polarization, which leads to a two-step process: (a) rapid domain switching (~1ns - 100ns) and (b) electron injection into the floating gate (~10μs - 1ms). This device can be potentially used as a dual-mode memory with a fast low-retention mode (DRAM), and a slower high-retention mode (Flash).

A unified circuit model for ferroelectrics

We present a physical circuit model for polarization reversal dynamics in ferroelectrics, which is implemented in Verilog-A, validated with PZT measurements and applicable in all operation modes for bulk, epitaxial and polycrystalline thin films. Consistent treatment of field-driven polarization not only gives accurate step-voltage responses across many decades in time, but also reproduces frequency and amplitude dependent P-E and I-V hysteresis loops for ferroelectric MIM capacitors. FE-RAM and gate-stack FE-FET circuit simulations are experimentally verified.

A hybrid ferroelectric and charge nonvolatile memory

We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.

Critical Assessment on Modeling and Design of Nonfaradaic CMOS Electrochemical Sensing

To assist the design process of nonfaradaic electrochemical sensors in realistic biological media, we examine multiple types of sensing operations in polyelectrolytes. By comparing the quasi-static transconductance, impedance spectroscopy, and capacitance-voltage measurements, we assess the physical contributions from the double-layer composition, overall solution resistance, and sensing surface potential under various polyelectrolytic molarities. The mixture of NaCl and MgCl2 is chosen for illustration to provide insight into circuit model parameters for nonfaradaic sensing. Our finding also shed light on the dynamics of double-layer competition and correlation, which is critical for understanding the physical phenomena occurring at the sensing interface, and accurately interpreting sensor data.