Frank Hawley

A Novel 65 nm Radiation Tolerant Flash Configuration Cell Used in RTG4 Field Programmable Gate Array

The newly introduced radiation-tolerant flash-based FPGA, RTG4, uses a novel configuration cell design composed of a NMOS switch controlled by a totem pole p-channel flash and n-channel flash construction. Its radiation tolerance is far superior to that in the present available Flash-based FPGA. This paper describes the radiation hardening by design (RHBD) process for the new flash-based configuration cell. A subtle and unique retention issue was found and resolved through studying physical mechanisms and conducting experiments.

High performance 65nm 2T-embedded Flash memory for high reliability SOC applications

High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD) and Gate Induced Drain Leakage current (GIDL) driven GD must be simultaneously studied to determine the optimum CG and SG spacing. For the applications requiring thick tunnel oxide (10nm) such as automotive products, the conductivities of the Sector Select Gate (SSG) device and Control Gate (CG) flash device are critical for read performance. A double SSG scheme per sector and common metal source line architecture were introduced. In this paper, we report our investigation results to optimize 2T eFlash cell design and array architecture to achieve high performance eFlash operation without sacrificing reliability within the constraint of embedding a flash process in the 65nm standard logic process.

Cycling impact on the Gm degradation and GIDL current of 65nm 2T-embedded Flash memory

Abnormal Gm degradation and GIDL current in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) is investigated. Severe charge trapping and de-trapping at the floating gate to junction overlap area lead to the endurance failure and cell current degradation. Control Gate (CG)-Select Gate (SG) Inter-junction trapping further degrades endurance and GIDL due to enhanced field and deeply depleted inter-junction. High temperature retention bake showed the charge relaxation and subsequent failure in the programmed cells. In this paper, we report both Gm and GIDL improvement of 2T eFlash memory with optimized gate-sidewall and extra thermal steps within the constraint of embedding flash process in the 65nm standard logic process.

Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through

Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID induced threshold-voltage shift and retention mechanisms are evaluated by analyzing test data.

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Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are reviewed. Long-chain inverter design is recommended for reliability evaluation because it can detect degradations of both programmable and erased Flash cells. All the reliability issues are unified and modeled by one natural decay equation.

Shift

We present a study on NBTI life time for high voltage PMOS transistors. These devices are used in erasing and programming control circuits for a floating-gate flash based FPGA array fabricated with a 65nm embedded process. NBTI stress tests were performed with different gate biases and at different temperatures. Life time model parameters, such as voltage acceleration factor and activation energy, were obtained from the tested results. NBTI device life time was assessed against product requirements. A 50 times (50X) margin in life time was estimated for our baseline process, based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or completely depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases. To further improve NBTI lifetime margin against product requirement, LDD doping was increased and optimized. We are able to further improve HV PMOS device performance in this regard.

Flash-Based FPGA TID and Long-Term Retention Reliability through VT Shift Investigation

In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat whereas hole trapping degrades Idsat. The effect of electron trapping and hole trapping cancel each other. As a result, life time is longer when two trapping mechanisms are involved compared with the life time with one trapping mechanism. In this study, device Idsat degradation was measured with different gate and drain biases in a DC mode. An AC stress is also performed in which gate/drain bias waveforms follow those of a typical switching inverter. Due to the above-mentioned cancelling effect, PMOS HCI AC life time is longer and the DC to AC conversion factor is much larger than conventionally used values. The effect of STI stress on HCI degradation is briefly studied. Layouts to minimize this effect are then proposed.

NBTI life time of a high voltage PMOS FET

We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.

Voltage dependence and AC life time of PMOS HCI

An antifuse structure was analyzed using scanning electron microscope imaging and focused ion beam image slicing to generate a form of three-dimensional microscopy. This method reveals nanometer scale features that could not be easily imaged using a single focused ion beam cross-section. A novel end-point detection technique has been developed to control the thickness of the slice to about 2 nm. Voxel imaging and interpretive three-dimensional reconstruction was used to resolve volumes as small as 2 cubic nm 3 . It was determined that the fusing region for an antifuse is a complex mixture of material phases with an elliptical volume approximately 75 nm in diameter.

High voltage PMOS FET NBTI results and mechanism

The single event effects hardening and heavy-ion testing of a radiation-hardened Flash-based field programmable gate array, RTG4, are presented. The hardened logic circuits include fabric flip-flops, fabric SRAM, global clocks, PLL, and SERDES. SEL is hardened for the whole chip. Lastly, the inspace programming is hardened as the consequence of the above hardening activities. Test results show the effects of hardenings.