Wenyi Feng

Reconfiguration of one-time programmable FPGAs with faulty logic resources

A comprehensive approach is given to reconfigure field programmable gate arrays (FPGAs) with faults in the logic resources. Reconfiguration consists of a reassignment of the cells that takes into account the one-time programmable nature of the chip resources. The method alters neither the FPGA nor the fault-free design; so the effectiveness of the reassignment depends on the efficient use of routing resources in the fault-free design. Under a generalized architecture, the spare routing resources needed are obtained to bypass each faulty cell and reassign its functions to a spare (unused) cell. If every channel has as many spare trades as half the number of logic cell inputs and outputs, then any single faulty cell can be reassigned, thus yielding a successful chip reconfiguration. The proposed reassignment algorithm has an efficient execution, so it can be run while chips are programmed and tested on an assembly line. The number of calls to the routing software is at worst quadratic in the number of faulty cells, provided no backtracking is needed in the reassignment. Under some randomness assumptions, the average number of calls to the routing software is linear in the number of faulty cells. The proposed method is analyzed with benchmark circuits and simulation results are presented.

Testing a Nanocrossbar for Multiple Fault Detection

This paper proposes an approach for testing a nanocrossbar switch; fault detection is considered in the presence of faulty switches and nets (of a permanent nature only) in the crossbar. To ensure detection, a one-to-one (onto) relationship in the setting (programming) of the switches is established in each of the configurations of the crossbar. This is accomplished using a constant-sum transformation of the characteristic matrix of the crossbar by utilizing different graph algorithms in O(N4.5) where N is the matrix dimension. Matrix properties are related to graph algorithms to generate permutation matrices as corresponding to the configurations (phases) of the crossbar. The conditions by which multiple faults are detected by the modified counting sequence (as test set), are proved. Simulation results are provided to further substantiate the validity of the proposed approach to test nanocrossbars of very large dimension and with different switch distribution.

Two-step algorithms for maximal diagnosis of wiring interconnects

We give two algorithms for maximal diagnosis of wiring networks without repair under a general fault model. Maximal diagnosis consists of identifying all diagnosable faults under the assumptions that each net can have multiple drivers and receivers and can be affected by any number of short and open faults. This process is equivalent to verifying all connections between inputs and outputs. Matrices represent the connections in fault-free and faulty networks. All algorithms discussed are adaptive and have their tests divided into two phases. Our first algorithm exploits a unique condition for verifying the connections; our second algorithm maps the connection verification problem to a bipartite graph. All algorithms use an independent test set for the first test phase. Simulation results show that the proposed algorithms outperform previous algorithms for maximal diagnosis, in terms of the number of tests. The total time complexity for computing the test sequences and analyzing the output response is polynomial.

Novel control pattern generators for interconnect testing with boundary scan

We give a comprehensive model of interconnect testing in boundary scan architectures. This includes two fault categories: driver faults (stuck-at, stuck-driving, and stuck-not-driving (equivalent to stuck-open)) and net faults (shorts). We permit short faults to exhibit zero-dominance (wired-AND), one-dominance (wired-OR), and net-dominance. We split the built-in self-test hardware into two components: a control pattern test generator (CTPG) and a data pattern test generator (DTPG). For the DTPG, we use a complementary counting sequence, which is an instance of a maximal independent test set. We give novel designs for CTPGs that guarantee 100% fault coverage with low hardware overhead and time complexity. We give a general and complete procedure to implement the CTPGs. Using a linear feedback shift register as a one-shot counter to cover all control cells in the boundary scan, we ensure that no two control cells of one net are assigned to a single register; this avoids circuit damage when testing.

Adaptive algorithms for maximal diagnosis of wiring interconnects

We give two algorithms for maximal diagnosis of wiring networks without repair under a general fault model. Maximal diagnosis consists of identifying all diagnosable faults under the assumptions that each net can have multiple drivers and receivers and can be affected by any number of short and open faults. This process is equivalent to verifying all connections between inputs and outputs. Matrices represent the connections in fault-free and faulty networks. We present two new algorithms and discuss prior algorithms. All algorithms discussed are adaptive and have their tests divided into two phases. Our first new algorithm exploits a unique condition for verifying the connections; our second new algorithm maps the connection verification problem to a bipartite graph. All algorithms discussed use an independent test set for the first test phase. Simulation results show that the proposed algorithms outperform previous algorithms for maximal diagnosis in terms of the number of tests. The total time complexity for computing the test sequences and analyzing the output response is polynomial.

Fault detection in a tristate system environment

Embedded computers commonly rely on multiple-board systems, called tristate system environments. These environments consist of an interconnect and drivers or receivers with tristate features and boundary scan capabilities. The authors present a comprehensive fault model that provides 100 percent fault coverage and minimizes test set size.

A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD

In this paper, a novel architecture for built-in self test (BIST) and different designs for both the control and data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity.

On the complexity of sequential testing in configurable FPGAs

This paper addresses the issues pertaining to testing field programmable gate arrays (FPGAs) using an array-based technique. In particular, the issues of testing configurable devices (such as multiplexers and flip-flops) in the sequential array process (as the most significant factor for assessing complexity) and the arrangement for pipelining test vectors are treated in detail. Initially testing procedures for a configurable flip-flop and a programmable multiplexer are presented. At system-level, two new pipeline arrangements referred to as the quasi-pipeline and normal pipeline structures are proposed for reducing the number of programming phases. The application of the proposed approaches to the XC4000 FPGA family is also presented.