Jone F. Chen

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFETs. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.

Design in hot-carrier reliability for high performance logic applications

Static (DC) and dynamic (AC) hot carrier degradation mechanisms were reviewed. Circuit performance degradation has been correlated to individual NMOS or PMOS device under DC stress. AC degradation model calibration and evaluation guidelines were also reviewed to ensure the use of hot-carrier reliability simulation tools at circuit level. As an example, thousand-hour inverter ring oscillator speed degradation data with different fanout, stress voltages, channel length, and processes are compared with that obtained from reliability simulation. The results show that reliability simulation is a powerful tool for logic circuit design optimization. It can predict the long-term circuit hot-carrier degradation accurately. The reliability of inverter, NAND, and NOR structures are also simulated and compared.

Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates

The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed V/sub dd/, asymmetric LDD devices exhibit higher I/sub dsat/ and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/ while higher I/sub dsat/ is retained. For the same hot-carrier lifetime, ring oscillators with NMOSFET asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power. The hot-carrier reliability of inverter, NAND, and NOR structures with asymmetric and conventional LDD devices is also simulated and compared.

Noise overshoot at drain current kink in SOI MOSFET

The bias dependence of the drain current noise power of SOI (silicon-on-insulator) MOSFETs was studied, and low frequency noise overshoot at the drain current was observed. The overshoot has a width of about 0.7 V and exhibits a peak noise power which is two orders of magnitude higher than the normal noise level. The SOI devices used in this study were N-channel polysilicon gate MOSFETs on SIMOX (separation by implantation of oxygen) wafers fabricated with conventional submicron CMOS technology. The SOI film thickness, the buried-oxide thickness, and the gate oxide are 100 nm, 300 nm, and 11.5 nm, respectively. A computer-controlled test system was used to conduct the I-V and noise measurement automatically. A model explaining the occurrence of the noise overshoot and the noise peak is proposed.<<ETX>>

Transient behavior of subthreshold characteristics of fully depleted SOI MOSFETs

It has been found that the subthreshold currents of fully depleted silicon-on-insulator (SOI) MOSFETs show a transient behavior under certain front-gate and back-gate voltage conditions. The cause of this anomaly is explained, and applications for the phenomenon are pointed out. Particularly, a simple way to measure the silicon film thickness is suggested.<<ETX>>

0.35-μm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology

The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I/sub dsat/ and larger I/sub sub/ TO maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V/sub dd/. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power.

An accurate model of thin film SOI-MOSFET breakdown voltage

A quantitative model which relates the SOI (silicon-on-insulator) MOSFET breakdown voltage to key parameters such as channel length, SOI film thickness, and gate voltage is presented. The SOI breakdown is caused by electron impact ionization current produced near the drain which is subsequently amplified by a parasitic lateral bipolar transition. This model is based on analytic modeling, quasi-2-D simulation and experimental study of the maximum drain electric field in SOI, and a novel method for measuring the lateral BJT (bipolar junction transistor) current gain beta using GIDL (gate-induced drain leakage) current. It can accurately model the breakdown voltage within 0.2 V for different channel lengths, gate voltages, and SOI film thicknesses.<<ETX>>

Hot electron gate current and degradation in P-channel SOI MOSFETs

I/sub G/ in P-channel SOI (silicon-on-insulator) MOSFETs is modeled and device degradation is characterized. It is found that E/sub m/ is about the same as in bulk devices. The SOI devices used in this study were p/sup +/ polysilicon gate P-channel MOSFETs fabricated using a modified submicron CMOS technology on SIMOX (Separation by IMplanted OXygen) wafers. It is shown that the peak degradation of both I/sub D/ and G/sub m/ occurs close to the I/sub g/ peak. This indicates that electron injection is the dominant mechanism for PMOS degradation in SOI and similar to bulk PMOS.<<ETX>>

Enhanced hot-carrier induced degradation in shallow trench isolated narrow channel PMOSFET's

Enhanced hot-carrier induced current degradation in narrow channel PMOSFETs with shallow trench isolation structure is observed. This phenomenon is not due to the increase in gate current, but the result of the increase in the electron trapping efficiency of the gate oxide. Mechanical stress may he responsible for the enhanced electron trapping efficiency.

Electromigration design rules for bidirectional current

Electromigration reliability of different metallization systems and structures under bidirectional current stress is studied in a wide frequency range (from mHz to 200 MHz). The experimental results show that at very low frequencies, the damage healing factor and lifetime under AC stress increases with increasing frequency. At high frequencies, the pure AC lifetime was found to be determined by the thermal migration instead of electromigration. All the observations are in agreement with an average current model indicating that while AC current contributes to self-heating, only the average (DC) current contributes to electromigration in all practical cases for interconnects and vias. The conclusion applies to all materials and geometries tested.