Shui-Hung Chen

Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance

Integrated circuit having improved ESD protection

Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM

Polycrystalline silicon diode string for ESD protection of different power supply connections

Robust latchup-immune CMOS structure

Modified source side inserted anti-type diffusion ESD protection device

Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM

ESD protection component

Integration method for deep sub-micron dual gate transistor design

Highly latchup-immune CMOS I/O structures