Jong-ho Lee

Board level reliability of novel Fan-in package on package(PoP)

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die Package - Dual Stack Package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die Package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.