Eun-Chul Ahn

Laser Dicing and Subsequent Die Strength Enhancement Technologies for Ultra-thin Wafer

Current mechanical wafer dicing process adopting diamond grit shows advantages of low cost and high productivity. However, mechanical process for ultra-thin wafers would induce residual stress or mechanical damage, which can lead to wafer broken and die cracking. With the development of laser technology, laser precision micromachining has been employed for thin semiconductor wafer singulation, which shows advantages of no chipping, small kerf width, and high throughput over mechanical blade dicing. However, thermal damage to the chip induced by laser ablation results in die strength degradation. For ultra thin chip, low die strength tends to induce die crack in packaging process. Thus, thermal damage to the chip needs to be studied. In this study, first we made a comparison between mechanical blade sawing and laser ablation processes. Die strength and microstructure changes were studied by means of bending test and transmission electron microscope (TEM) analysis, respectively. Die strength results showed that the die strength obtained by laser dicing was far lower than that obtained by blade sawing. TEM analysis demonstrated that formation of microcracks and porosities in laser diced face, caused the die strength degradation. In addition, significant deviation between frontside and backside die strength was found in the laser micromachinned dies. The reason for this deviation was clarified as the defects density difference existing in top and bottom layer of the chip sidewalk Experiments results showed that the die strength obtained by laser dicing can not meet the demand of the packaging process. It tends to crack or fracture in the die attach or wire bonding process. Thus, it is essential to improve the die strength. Thus, in this investigation, etching processes including wet-etch and dry-etch were attempted to recover the die strength by removing the chip side wall damage. SEM and TEM images indicated that, before etching, the laser diced side walls were with rough surfaces, voids and microcracks. After etching, the surfaces got smooth and most of the voids and microcracks were removed. Chip strength measurement also verified the partial die strength recovery after etching process.

Mechanisms of die and underfill cracking in flip chip PBGA package

This paper focuses on understanding the mechanisms of die and underfill cracking during MRT (Moisture Resistance Test, JEDEC level 3) and TCT (Thermal Cycling Test, -55-125/spl deg/C). A parametric study has been performed to understand the influence of die and substrate thickness, and metal attachment on die cracking. It is found that a combination of thinner die and thicker substrate leads to good results. In the case of metal stiffener attachment on die backside using low modulus adhesive, die cracking is eliminated. Underfill cracking can be categorized into three groups, popcorn cracking, corner cracking, and edge cracking. The popcorn and corner cracking originate from interfacial delamination between underfill and die passivation. Such cracking is improved by baking the organic substrate before the underfill process and by using high adhesion strength underfill. Since the mechanism of underfill edge cracking is very complicated, mechanical simulations and experiments are conducted to understand it. The authors conclude that underfill edge cracking is closely related to the local CTE mismatch between underfill material and silicon die, and can be eliminated by using low CTE underfill material and by control of underfill fillet size.

Improvement of drop reliability in OSP/Cu pad finished packages

This study investigated the improvement of drop reliability of OSP (organic solderability preservatives) pad finished packages having half etched solder ball pads. Besides the effect of the Cu pad etching depth, effects of other factors such as solder composition or reflow peak temperature on drop reliability were examined by the bending impact test and drop test. The bending impact test results showed that the increase of etching depth at the solder ball pad increased the drop reliability because of the fracture mode transition from solder/pad interface failure to solder bulk failure, but that the increase of reflow peak temperature decreased the drop reliability. The drop test results showed that the increase of the etching depth at the solder ball pad increased the drop reliability without the fracture mode transition, and that the change of the solder composition from Sn3.0Ag0.5Cu to Sn1.2Ag0.5Cu0.05Ni increased the drop reliability and shifted the fracture mode from interface failure to the bulk failure. The optimal conditions for the drop reliability improvement are presented in terms of the etching depth at the solder ball pad, the reflow peak temperature, and the solder composition.

Development of multi stack package with high drop reliability by experimental and numerical methods

Board level drop reliability of MSP (multi stack package) composed of a logic chipset package at bottom and an MCP (multi chip package) at top was investigated. The reliability of the package was tested by a developed drop (shock) tester. Applied shock level was half sine shape with 1500 G peak acceleration and 0.5 msec duration time. Failures were detected by four daisy chain loops going through solder balls and traces on each package. All failures were observed at the bottom chipset solder ball. The locations of failed balls were observed by dye and pry technology. The detailed physics of failure was observed by cross sectioning. EDX analysis was carried out at the failed IMC (inter-metallic compound) layer and brittle fracture between Cu6 Sn5 and Cu3Sn was observed. Fluctuation of the test board was measured by an accelerometer, strain gage, and gap sensor. A modal test was performed to measure the natural frequency of the board. Complex phenomena during the short period of the drop were analyzed by numerical simulation; finite element method. A simplified beam and shell model was adopted to obtain the global motion of the board, and a three-dimensional continuum sub model was adopted for the detail analysis of the ball. Both axial force and bending moment on the solder were good failure parameters. Local stress analysis showed stress concentration at the edge of a solder ball. Modal dynamic analysis gave similar result to real time analysis and its computation time was 1/6 of implicit analysis

Reliability of flip chip BGA package on organic substrate

In this paper various reliability issues of the flip chip package on organic substrate, such as the 1st level bump joint reliability, die cracking, underfill cracking, and 2nd level solder ball joint reliabilty, are primarily described. This paper discusses the reasons and resolutions of failures.

Development of chip scale package for DRAM

In order to assemble a chip scale package (CSP), a die with centralized bonding pads was mounted on a printed circuit board (PCB) using adhesive film, and was wire-bonded through a slot formed along the PCB center area, followed by encapsulation. After solder ball attachment, a PCB strip was divided into individual packages by punching. As the whole process is available with current equipment and materials, the assembly cost for this CSP is very low. The package height is lower than 1.0 mm, and the body size is larger than the die size only by 0.4 mm at each side. The ball pitch and size are 0.75 mm and 0.35 mm, respectively. The ball matrix was depopulated at the center area by two rows, leaving sufficient space for wire bonding. The package has passed reliability tests, including the level 3 preconditioning test, 240 hours of pressure cooker tests, and 1000 cycles of temperature cycling at board level as well as at component level. Through this work, it was has been verified that this CSP is one of the most cost-effective CSP solutions for DRAM devices.

Characterization of Wire Bondability on Overhang Structured Chip in Multi Chip Package

Characteristics of wire bonding on the overhang structured chip were investigated in this study. During the wire bonding process, chip crack and bondability were severe factors for thin wafer bonding. Chip crack was investigated by chip strength test and parametric study was performed by changing bonding parameters, constant velocity, force, and power. Bondability was measured for 500, 700, and 1000 mum overhang length. Bonding strength was tested by ball shear test method. 700 mum overhang showed better performance than 500 mum. 1000 mum overhang showed very low bondability. Bonding characteristics were observed by numerical FEM method. Nonlinear dynamic analysis was performed. Unstable contact pressure and shear stress were observed between ball and metal pad. Noise of reaction force was increased with overhang length.

Board level reliability of novel Fan-in package on package(PoP)

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die Package - Dual Stack Package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die Package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.

Effect of Ni Surface Finish on Half Etched Cu on Solder Joint Reliability

Thermal cycling (TC) and drop test results of electronic package are presented in this paper, which have been known as the main reliability test items in electronics. Especially, as the movement of personal computer to handhelds accelerates, this paper focused on concurrent requirements for TC and drop reliability. The research was carried out by the modification of current solder pad finish and the comparative test results were represented. Considered that OSP on half etched Cu was normally used in mobile package, Ni/Au finish on half etched Cu was applied in this work. SnAgCu solder ball was used, and Ni/Sn on half etched Cu was also evaluated as Sn plating is used in some applications. Test results showed that Ni/Au finish on half etched Cu can be one of solutions to satisfy TC and drop reliability simultaneously.