Young-Lyong Kim

Structural Stability and Phase-Change Characteristics of Ge2Sb2Te5 ∕ SiO2 Nano-Multilayered Films

The phase-change characteristics of Ge 2 Sb 2 Te 5 /SiO 2 multilayered films with various bilayer thicknesses were investigated using high-resolution transmission electron microscopy. The change in the electrical sheet resistance of the films shows that the metastable face-centered cubic (fcc) structure formation was significantly affected by the bilayer thickness of the multilayer film. That is, compared with the single-layered Ge 2 Sb 2 Te 5 film, the multilayered films transformed to hexagonal at lower temperatures. In particular, the transition temperature region of the fcc structure with semiconductor properties was significantly reduced. We observed that as the bilayer thickness decreased and annealing temperature increased, the structure of the multilayer film was transformed into Ge-deficient and hexagonal phases such as GeSb 2 Te 4 and Sb 2 Te 3 . This behavior was induced by the out-diffusion of Ge atoms from the outer surface layer, which can be caused by a difference in thermal strain at the interface between the Ge 2 Sb 2 Te 5 and SiO 2 films.

Electronic and structural characteristics of Zr-incorporated Gd2O3 films on strained SiGe substrates

Zr-incorporated Gd(2)O(3) films were grown on various substrates as a function of Zr content. The extent of interfacial reactions was found to be critically dependent on both the incorporated Zr content and the substrate type. Specifically, the silicide layer was suppressed and the Gd(2)O(3) phase was changed to ZrO(2) on a Si substrate with increasing Zr content. Crystalline Gd(2)Ge(2)O(7) was grown on a Ge substrate, as the result of interfacial reactions between Gd-oxide and the Ge substrate. However, interfacial reactions were not affected by the amount of Zr incorporated. On the SiGe/Si substrate, reactions between Gd-oxide and Si could be controlled effectively by the incorporation of Zr, while the extent of reactions with Ge was significantly enhanced as the Zr content increased. The formation of an interfacial layer between the film and the SiGe substrate resulted in a textured crystalline growth.

Board level reliability of novel Fan-in package on package(PoP)

The recent requirements for achieving higher memory density in a smaller package size have adopted 3D packaging of thin dies in a single package. However, increasing the number of dies in 3D stacking is limited by increasing the cost due to decrease die stacking yield. The known good package stacking can be solution to overcome such yield loss. In this study, a novel Fan-in PoP solution proposed, stacking two package which have stacked multiple dies each and interconnecting the package through blind EMC via without changing package size. The solder ball of top package fills up the blind EMC via during the reflow process. In order to evaluate the board level reliability, Fan-in PoP(QDP-DSP : Quad Die Package - Dual Stack Package) was mounted to a FR-4 board. Fan-in PoP with various solder compositions wes explored regarding the failure mode, crack propagation and life time under the drop test and thermal cycling test compared to those of ODP (Octa Die Package). The Fan-in PoP showed superior drop performance compared to ODP due to the package flexibility. On the other hand, thennal cycling test results showed a little increased life time compared to ODP. The solder joint formation on the silicon chip through blind EMC via causes the serious thermal stress concentration due to the silicon stiffness.