Jong-Hyon Ahn

The effect of body contact arrangement on thin SOI MOSFET characteristics

Abstract Several body contact arrangement types have been studied to improve the parasitic phenomena such as the edge transistor effect and the bipolar action. The H-gate SOI MOSFET with the body contacts at both ends of channel was found to be most effective to suppress the edge transistor effect and reduce the drain leakage current and the bipolar action.

1 GHz microprocessor integration with high performance transistor and low RC delay

This paper describes the process that enabled the development of the worlds first 1 GHz microprocessor that was implemented with 6-layer Al interconnections, low-k dielectrics as the interlayer materials to reduce RC delay, and high-performance transistors having L/sub eff/ of 0.1 /spl mu/m. These enhancements were the key in producing the 1 GHz 64-bit RISC microprocessor that operates at 1.9 V and 80/spl deg/C at which the junction temperature is measured at 135/spl deg/C.

Device Performance Improvement Based on Transient Enhanced Diffusion Suppression in the Deep Sub-Quarter Micron Scale

In the deep sub-quarter micron scale, the transient enhanced diffusion (TED) of the gate channel region gives rise to the variation of device characteristics due to the influence of interstitial silicon atoms generated by the extension ion implantation damage. The channel impurity variation caused by TED becomes a dominant factor and brings about a more severe fluctuation of the threshold voltage (Vth) than the physical gate channel length (Lgate) or the gate-oxide (Gox) thickness variation does. This work presents the results of suppressing the reverse short channel effect (RSCE) which is shown due to TED by using the local channel implantation process. In the case of using a boron source as an n-type channel (n-channel) dopant, the 10% improvement of the RSCE and the 70% reduction of the Vth fluctuation are achieved through TED suppression by rapid thermal anneal (RTA) treatment. Furthermore, we not only demonstrates the 15% increase of the current driving capability but also clearly removes the RSCE by realizing the super-steep retrograded (SSR) channel doping profile with an indium species as the n-channel dopant and adopting RTA process.

High performance 0.18 um nMOSFET by TED suppression

In deep sub-quarter micron, Transient Enhanced Diffusion (TED) of gate channel (Lgate) region seriously gives rise to the variation of device characteristics due to the increase of interstitial silicon atoms. Channel impurity variation by this TED becomes more dominant factor to bring about the severe fluctuation of threshold voltage than the gate length or the gate oxide thickness variation does. This work presents the results of suppressing Reverse Short Channel Effect (RSCE) which severely is showed in the selectively implanted channel process using local implant process. In case of using boron as the n-channel dopant, the 10% improvement of RSCE and the 35% reduction of Vth fluctuation are achieved through TED suppression by Rapid Thermal Anneal (RTA) treatment. We not only demonstrated the 15% increase of current drive but also removed RSCE clearly by realizing of Super-Steep Retrograded (SSR) channel doping profile with indium.

Series resistance at metal contact for thin film SOI MOSFET

Thin-film silicon-on-insulator (TFSOI) MOSFET has emerged as a strong candidate for high performance, high density and latch-up free CMOS devices with less fabrication steps. Thin silicon film should be used to achieve good behavior in SOI MOSFET. However, most of the papers on TFSOI have reported high parasitic source/drain series resistance and contact resistance, which tends to obscure the performance advantages of SOI. In this paper, we examined effects of top silicon film thickness (Tsi) on contact series resistance and contact hole etching method.