Soo-Cheol Lee

1 GHz microprocessor integration with high performance transistor and low RC delay

This paper describes the process that enabled the development of the worlds first 1 GHz microprocessor that was implemented with 6-layer Al interconnections, low-k dielectrics as the interlayer materials to reduce RC delay, and high-performance transistors having L/sub eff/ of 0.1 /spl mu/m. These enhancements were the key in producing the 1 GHz 64-bit RISC microprocessor that operates at 1.9 V and 80/spl deg/C at which the junction temperature is measured at 135/spl deg/C.

Comparative Study of Process Window Identification Methods for 45 nm Device and Beyond

Lithography process control becomes increasingly challenging as the design rules shrink. To tackle the issue of identifying the process window for lithography, we systematically compared three different approaches for 45 nm process wafer with two variables: Inspection mode (FEM or PWQ) and Analysis methodology (Manual or Design Based Binning). We found that PWQ + DBB provided the best results.

Degradation phenomenon of p+ to p+ isolation characteristics caused by carrier injection in a high-voltage process

In this study, an investigation for the degradation of p+ to p+ isolation characteristics in a high voltage process with shallow trench isolation was carried out. It could be explained that the degradation phenomenon was caused by carrier injection. In order to improve this, the results of p+ to p+ isolation degradation were determined under different ion implantation conditions and depths and widths of isolation. From these results, it was found that carrier injection mainly occurred at the sidewall of a trench, and the interface trap between Si3N4 and SiO2 was considered to be a dominant factor based on the result of degradation reduction with increasing thickness of sidewall oxide. Consequently, the improvement of the p+ to p+ isolation degradation caused by carrier injection could be achieved by optimizing the dose of a masked lightly doped drain and a field implantation energy.

Carbonized surface curing for etch-back process

For flash memory below the 63nm node, two step Undoped Silicon Glass (USG) deposition and one step etch-back processes are applied in manufacturing processes to get good gap fill properties for Shallow Trench Isolation (STI) structures. The characteristics of the silicon surface after an etch-back process influences the following second USG deposition thickness and variation because the USG deposition process has high under-layer dependency and surface sensitivity. It can be reduced by changing some parameters during the deposition process like O3-TEOS ratio or temperature or pressure, but these methods also change the gap fill property and deposition rate [1]. So, we should find another method. This paper presents the detail studies of surface characteristics during processes that have been carried out to optimize the USG etch-back process.

Novel method to generate inspection care areas using GDS

In order to make wafer inspection more sensitive, it is necessary to create inspection care areas that better reflect the actual layout of features in each die. However, it is very time consuming and tedious to draw such care areas manually. In this work, we proposed a novel method to generate suitable care areas using GDS. Two innovative ways were developed and enabled this method to be implemented in a mass production.

Device Performance Improvement Based on Transient Enhanced Diffusion Suppression in the Deep Sub-Quarter Micron Scale

In the deep sub-quarter micron scale, the transient enhanced diffusion (TED) of the gate channel region gives rise to the variation of device characteristics due to the influence of interstitial silicon atoms generated by the extension ion implantation damage. The channel impurity variation caused by TED becomes a dominant factor and brings about a more severe fluctuation of the threshold voltage (Vth) than the physical gate channel length (Lgate) or the gate-oxide (Gox) thickness variation does. This work presents the results of suppressing the reverse short channel effect (RSCE) which is shown due to TED by using the local channel implantation process. In the case of using a boron source as an n-type channel (n-channel) dopant, the 10% improvement of the RSCE and the 70% reduction of the Vth fluctuation are achieved through TED suppression by rapid thermal anneal (RTA) treatment. Furthermore, we not only demonstrates the 15% increase of the current driving capability but also clearly removes the RSCE by realizing the super-steep retrograded (SSR) channel doping profile with an indium species as the n-channel dopant and adopting RTA process.

High performance 0.18 um nMOSFET by TED suppression

In deep sub-quarter micron, Transient Enhanced Diffusion (TED) of gate channel (Lgate) region seriously gives rise to the variation of device characteristics due to the increase of interstitial silicon atoms. Channel impurity variation by this TED becomes more dominant factor to bring about the severe fluctuation of threshold voltage than the gate length or the gate oxide thickness variation does. This work presents the results of suppressing Reverse Short Channel Effect (RSCE) which severely is showed in the selectively implanted channel process using local implant process. In case of using boron as the n-channel dopant, the 10% improvement of RSCE and the 35% reduction of Vth fluctuation are achieved through TED suppression by Rapid Thermal Anneal (RTA) treatment. We not only demonstrated the 15% increase of current drive but also removed RSCE clearly by realizing of Super-Steep Retrograded (SSR) channel doping profile with indium.