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Dive into the research topics where You-Seung Jin is active.

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Featured researches published by You-Seung Jin.


international reliability physics symposium | 2004

Negative bias temperature instability in triple gate transistors

Shigenobu Maeda; Jung-A Choi; Jeong-Hwan Yang; You-Seung Jin; Su-Kon Bae; Young-Wug Kim; Kwang-Pyuk Suh

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The <100>-direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.


symposium on vlsi technology | 2004

Impact of mechanical stress engineering on flicker noise characteristics

Shigenobu Maeda; You-Seung Jin; Jung-A Choi; Sun-Young Oh; Hyun-Woo Lee; Jae-yoon Yoo; Min-Chul Sun; Ja-hum Ku; Kwon Lee; Su-Gou Bae; S. K. Kang; Jeong-Hwan Yang; Young-Wug Kim; Kwang-Pyuk Suh

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.


international electron devices meeting | 2003

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

Jeong-Hwan Yang; You-Seung Jin; Hyae-ryoung Lee; Kyoung-Seok Rha; Jung-A Choi; Su-Kon Bae; Shigenobu Maeda; Young-Wug Kim; Kwang-Pyuk Suh

Fully working 1.25 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology. This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported.


international electron devices meeting | 2011

A 192×108 pixel ToF-3D image sensor with single-tap concentric-gate demodulation pixels in 0.13 µm technology

Tae-Yon Lee; Y. J. Lee; Dong-Ki Min; S.H. Lee; Won-joo Kim; Sung Hwan Kim; Jongwan Jung; Ilia Ovsiannikov; You-Seung Jin; Young-soo Park; Eric R. Fossum; Chilhee Chung

A single-tap concentric photogate pixel of 28 µm pitch is developed for application to time-of-flight (ToF) three dimension (3D) image sensors. The 198×108 ToF pixel array exhibits demodulation contrast higher than 50% and distance error less than 1%, over 1 to 7 m range using 20MHz modulation of 850 nm light emitting diode (LED) illumination.


Archive | 2003

Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof

You-Seung Jin; Jong-Hyon Ahn


Archive | 2012

Semiconductor device, method of manufacturing the semiconductor device, flip chip package having the semiconductor device and method of manufacturing the flip chip package

Se-young Lee; You-Seung Jin; Geon-Woo Park


Archive | 2008

Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same

Choel-hwyi Bae; Jin-Hee Kim; You-Seung Jin; Dong-Hun Lee


Archive | 2005

Multi-gate transistor formed with active patterns of uniform critical dimension

You-Seung Jin


Archive | 2005

MOSFET and method of fabricating the same

You-Seung Jin; Jong-Hyon Ahn


Archive | 2008

Methods for identifying an allowable process margin for integrated circuits

Choel-hwyi Bae; You-Seung Jin

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